Coupled loop and void structure integrated in a redistribution layer of a chip package
Disclosed herein is a chip package and method for fabricating the same are provided that includes a redistribution layer (RDL) with a plurality of loop and void structures. The chip package includes an integrated circuit (IC) die, and a package substrate. The RDL is disposed between the IC die and the package substrate. The RDL has RDL circuitry that connects the IC die to the package substrate. The RDL circuitry includes a first coil formed in a first metal layer and a second coil formed in a second metal layer. A first end of the second coil is coupled to a second end of the first coil by a first via. A second end of the second coil is the IC die.
1. A chip package comprising:
an integrated circuit (IC) die;
a package substrate having a die side and a ball side; and
a redistribution layer (RDL) disposed between the IC die and the die side of the package substrate, the RDL comprising a plurality of conductive layers patterned to form RDL circuitry within the RDL, the RDL circuitry connecting the IC die to the package substrate; wherein the plurality of conductive layers forming the RDL circuitry further comprise:
a first metal layer having a first contact pad coupled to a first trace, the first trace arranged in a first coil, a first end of the first coil coupled to the first contact pad; and
a second metal layer having a second trace, the second trace arranged in a second coil, a first end of the second coil coupled to a second end of the first coil by a first via, wherein an opening is formed in the second metal layer that at least partially surrounds the second coil.
2. The chip package of claim 1 , comprising:
a plurality of apertures in the second metal layer, wherein at least a portion of the plurality of apertures are formed adjacent the opening that surround the second coil.
3. The chip package of claim 1 , comprising:
a solder ball disposed on the first contact pad.
4. The chip package of claim 1 , wherein the RDL further comprises:
a third metal layer having bond pads connected to contact pads of the IC die and to the second coil.
5. The chip package of claim 1 , wherein the first coil overlaps the second coil.
6. The chip package of claim 5 , wherein the first coil is aligned over the second coil.
7. The chip package of claim 5 , wherein the first coil and the second coil turn in a same direction.
8. The chip package of claim 1 , wherein the first coil has square turns around a center of the first coil.
9. The chip package of claim 1 , wherein the first coil is a spiral around a center of the first coil.
10. The chip package of claim 1 , wherein the first coil has at least 1.5 full turns around a center of the first coil.
11. The chip package of claim 1 , further comprising:
a second contact pad and an inductor structure disposed adjacent the first coil and forming routing for half of a differential signal pair.
12. The chip package of claim 11 , wherein the differential signal pair is symmetrical about a midpoint between the first contact pad and the second contact pad.
13. The chip package of claim 1 , wherein the RDL contacts a bottom of the IC die.
14. The chip package of claim 1 , wherein the RDL contacts a top of the package substrate.
15. The chip package of claim 1 , wherein the RDL contacts an interposer disposed between the IC die and the package substrate.
16. A chip package comprising:
an integrated circuit (IC) die;
a package substrate having a die side and a ball side; and
a redistribution layer (RDL) disposed between the IC die and the die side of the package substrate, the RDL comprising at least a first conductive layer and a second conductive layer that are patterned to form RDL circuitry within the RDL, the RDL circuitry connecting the IC die to the package substrate; wherein the RDL circuitry further comprise:
a first metal layer having a first plurality of apertures, and a first contact pad coupled to a first trace, the first trace arranged in a first coil, a first end of the first coil coupled to the first contact pad; and
a second metal layer having a second plurality of apertures, and a second trace, the second trace arranged in a second coil, a first end of the second coil coupled to a second end of the first coil by a first via, wherein an opening is formed in the second metal layer that at least partially surrounds the second coil.
17. The chip package of claim 16 , comprising:
a solder ball disposed on the first contact pad.
18. The chip package of claim 16 , comprising:
a third metal layer having bond pads connected to contact pads of the IC die.
19. The chip package of claim 16 , wherein the first coil overlaps the second coil.
20. The chip package of claim 19 , wherein the first coil and the second coil turn in a same direction.