Memory devices having source lines directly coupled to body regions and methods
Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body region to a source line. Configurations and methods shown should provide a reliable bias to a body region for memory operations such as erasing.
1. A memory device, comprising:
an elongated body region of the same conductivity type, having a source region coupled to a first end, and a drain region coupled to a second end;
a plurality of gates along a length of the elongated body region, each of the plurality of gates being separated from the elongated body region by at least a charge storage structure; and
a metal source line, wherein the first end of the elongated body region coupled to the metal source line by a portion of the elongated body region that passes through the source region.
2. The memory device of claim 1 , wherein the metal source line includes tungsten.
3. The memory device of claim 1 , wherein the elongated body region is oriented vertically.
4. The memory device of claim 1 , further including a first select gate adjacent to the first end of the elongated body region.
5. The memory device of claim 4 , further including a second select gate adjacent to the second end of the elongated body region.
6. A NAND memory device, comprising:
a vertical elongated body region, having a source region coupled to a first end, and a drain region coupled to a second end;
a plurality of gates along a length of the vertical elongated body region, each of the plurality of gates being separated from the vertical elongated body region by at least a charge storage structure; and
a metal source line, wherein the first end of the vertical elongated body region coupled to the metal source line by a portion of the body region that passes through the source region.
7. The NAND memory device of claim 6 , wherein the vertical elongated body region is a p-type body region.
8. The NAND memory device of claim 7 , wherein the source region is an n-type source region.
9. The NAND memory device of claim 6 , wherein the metal source line includes tungsten.
10. The NAND memory device of claim 6 , further including a first select gate adjacent to the first end of the elongated body region.
11. The NAND memory device of claim 10 , further including a second select gate adjacent to the second end of the elongated body region.
12. An electronic device, comprising:
a processor;
a memory device coupled to the processor, the memory device including:
an elongated body region of the same conductivity type, having a source region coupled to a first end, and a drain region coupled to a second end;
a plurality of gates along a length of the elongated body region, each of the plurality of gates being separated from the elongated body region by at least a charge storage structure;
a metal source line, wherein the first end of the elongated body region coupled to the metal source line by a portion of the elongated body region that passes through the source region; and
a display device configured to display information from the processor and the memory device.
13. The electronic device of claim 12 , wherein the metal source line includes tungsten.
14. The electronic device of claim 12 , wherein the elongated body region is oriented vertically.
15. The electronic device of claim 12 , further including a first select gate adjacent to the first end of the elongated body region.
16. The electronic device of claim 15 , further including a second select gate adjacent to the second end of the elongated body region.