Command and address sequencing in parallel with data operations

1. A method of performing a command/address sequence associated with a read/write operation for a memory device, the method comprising:

detecting a first enable signal;

detecting a first data signal;

responsive to detecting the first enable signal, latching, at each of a first one or more rising or falling edges of a clock signal, a bit value encoded in the first data signal to obtain a first bit pattern;

latching, at each of a second one or more rising or falling edges of the clock signal, a bit value encoded in the first data signal to obtain a second bit pattern;

decoding the first bit pattern as a second enable signal; and

decoding the second bit pattern as one of a command code and an address code.

2. The method of claim 1 , wherein the command/address sequence is performed in parallel with a data in (DIN) or data out (DOUT) operation.

3. The method of claim 2 , further comprising:

receiving the first data signal on a first data bus; and

receiving a second data signal for the DIN or DOUT operation on a second data bus.

4. The method of claim 3 , wherein the second data bus is an n-bit signal data bus and the first data bus is an m-bit signal data bus, wherein n and m are integers and m is less than n.

5. The method of claim 1 , wherein the first data signal is a 1-bit data signal.

6. The method of claim 1 , wherein the second enable signal is a command latch enable signal, and the second bit pattern is a command code.

7. The method of claim 1 , wherein the second enable signal is an address latch enable signal, and the second bit pattern is an address code.

8. The method of claim 1 , further comprising:

latching, at each of a third one or more rising or falling edges of a clock signal, a bit value encoded in the first data signal to obtain a third bit pattern;

latching, at each of a fourth one or more rising or falling edges of the clock signal, a bit value encoded in the first data signal to obtain a fourth bit pattern;

decoding the third bit pattern as third enable signal; and

decoding the fourth bit pattern as one of a command code and an address code.

9. A memory device, comprising:

one or more signal generators configured to generate a first enable signal, a second enable signal, and a clock signal; and

a controller configured to:

detect a first enable signal;

detect a first data signal;

responsive to detecting the first enable signal, latch, at each of a first one or more rising or falling edges of a clock signal, a bit value encoded in the first data signal to obtain a first bit pattern;

latch, at each of a second one or more rising or falling edges of the clock signal, a bit value encoded in the first data signal to obtain a second bit pattern;

decode the first bit pattern as a second enable signal; and

decode the second bit pattern as one of a command code and an address code.

10. The memory device of claim 9 , wherein the command/address sequence is performed in parallel with a data in (DIN) or data out (DOUT) operation.

11. The memory device of claim 10 , further comprising:

receiving the first data signal on a first data bus; and

receiving a second data signal for the DIN or DOUT operation on a second data bus, distinct.

12. The memory device of claim 11 , wherein the second data bus is an n-bit signal data bus and the first data bus is an m-bit signal data bus, wherein n and m are integers and m is less than n.

13. The memory device of claim 9 , wherein the first data signal is a 1-bit data signal.

14. The memory device of claim 9 , wherein the second enable signal is a command latch enable signal, and the second bit pattern is a command code.

15. The memory device of claim 9 , wherein the second enable signal is an address latch enable signal, and the second bit pattern is an address code.

16. The memory device of claim 9 , further comprising:

latching, at each of a third one or more rising or falling edges of a clock signal, a bit value encoded in the first data signal to obtain a third bit pattern;

latching, at each of a fourth one or more rising or falling edges of the clock signal, a bit value encoded in the first data signal to obtain a fourth bit pattern;

decoding the third bit pattern as third enable signal; and

decoding the fourth bit pattern as one of a command code and an address code.

17. A system, the system comprising:

a first memory array;

a second memory array;

a controller;

a first memory interface between the first memory array and the controller, the first memory array comprising an 8-bit signal data bus and a control bus, the first memory interface configured to:

detect a first enable signal on the control bus; and

responsive to the first enable signal, detect a first data signal over the 8-bit signal data bus, wherein the first data signal is encoded with data for one of a data in (DIN) and data out (DOUT) operation on the first memory array; and

a second memory interface between the second memory array and the controller, the second memory interface comprising at least one 1-bit signal data bus, the second memory interface configured to, in parallel with the first memory interface:

detect a second enable signal on the 1-bit signal data bus; and

responsive to the second enable signal, detect a second data signal on the 1-bit signal data bus, wherein the second data signal is encoded with a first bit pattern representative of a third enable signal and a second bit pattern representative of at least one of a command code and an address code.

18. The system of claim 17 , wherein the first bit pattern is encoded in the second data signal prior to the second bit pattern.

19. The system of claim 17 , wherein the third enable signal is a command enable signal and the first bit pattern is a command code.

20. The system of claim 19 , wherein the second data signal is further encoded with:

a third bit pattern representative of an address enable signal; and

a fourth bit pattern representative of an address code.