Systems and methods for reducing standby power in floating body memory devices
Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.
1. A semiconductor memory array configured for reducing standby power, said array comprising:
a plurality of floating body memory cells each having at least two stable floating body charge levels, wherein said floating body charge levels are maintained by a vertical bipolar holding mechanism; and
means for periodically turning off and on said vertical bipolar holding mechanism to reduce standby power of said floating body memory cells.
2. The semiconductor memory array of claim 1 , wherein each of said plurality of floating body memory cells further comprises a floating body region having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type.
3. The semiconductor memory array of claim 2 , wherein each of said plurality of floating body memory cells further comprises a back-bias region having a second conductivity type selected from said p-type conductivity type and said n-type conductivity type, wherein said second conductivity type is different from said first conductivity type.
4. The semiconductor memory array of claim 3 , wherein applying a back-bias to said back-bias region results in maintenance of said stable floating body charge levels.
5. The semiconductor memory array of claim 4 , wherein said back-bias is a constant positive voltage bias.
6. The semiconductor memory array of claim 4 , wherein said back-bias is a periodic pulse of positive voltage.
7. The semiconductor memory array of claim 1 , further comprising at least one reference cell to determine a period for said periodically turning off and on said vertical bipolar holding mechanism.
8. The semiconductor memory array of claim 7 , further comprising level detectors to determine said stable floating body charge levels.
9. A system for reducing standby power, said system comprising:
a plurality of floating body memory cells each having at least two stable floating body charge levels, wherein said stable floating body charge levels are maintained by a vertical bipolar holding mechanism;
and
a controller configured to periodically turning off and on said vertical bipolar holding mechanism to reduce standby power of said floating body memory cells.
10. The system of claim 9 , wherein each of said plurality of floating body memory cells further comprises a floating body region having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type.
11. The system of claim 10 , wherein each of said plurality of floating body memory cells further comprises a back-bias region having a second conductivity type selected from said p-type conductivity type and said n-type conductivity type, wherein said second conductivity type is different from said first conductivity type.
12. The system of claim 11 , wherein applying a back-bias to said back-bias region results in maintenance of said stable floating body charge levels.
13. The system of claim 12 , wherein said back-bias is a constant positive voltage bias.
14. The system of claim 12 , wherein said back-bias is a periodic pulse of positive voltage.
15. The system of claim 9 , further comprising at least one reference cell to determine a period for said periodically turning off and on said vertical bipolar holding mechanism.
16. The system of claim 15 , further comprising level detectors to determine said floating body charge levels.