Forming low-resistance capping layer over metal gate electrode
A semiconductor device includes stacks of nano-structures that each extend in a first horizontal direction. The stacks each extend in a vertical direction and are separated from one another in a second horizontal direction. A first gate is disposed over a first subset of the stacks. A second gate is disposed over a second subset of the stacks. A first conductive capping layer is disposed over a substantial entirety of an upper surface of the first gate. A second conductive capping layer is disposed over a substantial entirety of an upper surface of the second gate. A dielectric structure is disposed between the first gate and the second gate in the second horizontal direction. The dielectric structure physically and electrically separates the first gate and the second gate. An upper surface of the dielectric structure is substantially free of having the first or second conductive capping layers disposed thereon.
1. A device, comprising:
a plurality of stacks of nano-structures, wherein the nano-structures each extend in a first horizontal direction, wherein the stacks each extend in a vertical direction and are separated from one another in a second horizontal direction different from the first horizontal direction;
a first gate structure disposed over a first subset of the stacks of nano-structures, wherein the first gate structure surrounds each of the nano-structures in the first subset;
a second gate structure disposed over a second subset of the stacks of nano-structures, wherein the second gate structure surrounds each of the nano-structures in the second subset;
a first conductive capping layer disposed over a substantial entirety of an upper surface of the first gate structure;
a second conductive capping layer disposed over a substantial entirety of an upper surface of the second gate structure; and
a dielectric structure disposed between the first gate structure and the second gate structure in the second horizontal direction, wherein the dielectric structure physically and electrically separates the first gate structure and the second gate structure, and wherein an upper surface of the dielectric structure is substantially free of having the first conductive capping layer or the second conductive capping layer disposed thereon.
2. The device of claim 1 , wherein the dielectric structure includes a cut-metal-gate (CMG) structure that contains a single type of dielectric material.
3. The device of claim 1 , wherein the dielectric structure includes a dielectric fin structure that contains multiple types of dielectric materials.
4. The device of claim 1 , a gate via disposed over the first conductive capping layer or over the second conductive capping layer, wherein a dimension of the gate via measured in the second horizontal direction is substantially less than a dimension of the first conductive capping layer or the second conductive capping layer measured in the second horizontal direction.
5. The device of claim 4 , wherein the dimension of the first conductive capping layer or the second conductive capping layer is at least multiple times greater than the dimension of the gate via.
6. The device of claim 4 , wherein the first conductive capping layer and the second conductive capping layer each have a lower resistivity than the gate via, the first gate structure, and the second gate structure.
7. The device of claim 1 , further comprising a source/drain contact and a gate spacer structure, wherein the gate spacer structure physically and electrically separates the source/drain contact from the first conductive capping layer or from the second conductive capping layer in the first horizontal direction.
8. The device of claim 1 , wherein the first conductive capping layer and the second conductive capping layer each contain tungsten.
9. The device of claim 1 , wherein:
the first gate structure and the second gate structure each include a respective metal-containing gate electrode; and
the first conductive capping layer or the second conductive capping layer has a lower resistivity than the metal-containing gate electrode.
10. The device of claim 1 , wherein in a cross-sectional view defined by the first horizontal direction and the vertical direction, a bottom surface of the first conductive capping layer or the second conductive capping layer includes one or more recesses.
11. The device of claim 10 , wherein:
the first gate structure or the second gate structure includes one or more non-conductive layers; and
the one or more recesses are located directly over the one or more non-conductive layers.
12. The device of claim 1 , further comprising a glue layer disposed between the first conductive capping layer and the first gate structure or between the second conductive capping layer and the second gate structure, wherein the glue layer defines a recess in a cross-sectional view defined by the first horizontal direction and the vertical direction, and wherein the conductive capping layer is disposed within the recess in the cross-sectional view.
13. A device, comprising:
a first stack of semiconductive nano-structures, wherein the semiconductive nano-structures in the first stack are disposed over one another in a vertical direction in a cross-sectional side view;
a second stack of semiconductive nano-structures, wherein the semiconductive nano-structures in the second stack are disposed over one another in the vertical direction in the cross-sectional side view;
a first gate that circumferentially surrounds the first stack of semiconductive nano-structures in the cross-sectional side view;
a second gate that circumferentially surrounds the second stack of semiconductive nano-structures in the cross-sectional side view;
a first conductive layer disposed over a substantial entirety of an upper surface of the first gate in the cross-sectional side view;
a second conductive layer disposed over a substantial entirety of an upper surface of the second gate in the cross-sectional side view; and
an electrically insulating structure disposed between the first gate and the second gate, and between the first conductive layer and the second conductive layer, in the cross-sectional side view.
14. The device of claim 13 , wherein no portion of the first conductive layer or the second conductive layer is disposed on an uppermost surface of the electrically insulating structure in the cross-sectional side view.
15. The device of claim 13 , wherein an uppermost surface of the electrically insulating structure is wider than a bottommost surface of the electrically insulating structure in the cross-sectional side view.
16. The device of claim 13 , further comprising a gate via disposed over the first conductive layer;
wherein:
the first conductive layer has a lower resistivity than the gate via; or
the first conductive layer is at least multiple times wider than the gate via in the cross-sectional side view.
17. The device of claim 16 , wherein the first conductive layer has a lower resistivity than the gate via.
18. The device of claim 16 , wherein the first conductive layer is at least multiple times wider than the gate via in the cross-sectional side view.
19. The device of claim 13 , wherein:
the first gate has a gate electrode component; and
the first conductive layer or the second conductive layer has a lower resistivity than the gate electrode component.
20. The device of claim 13 , wherein the electrically insulating structure has a different depth than the first gate or the second gate in the cross-sectional side view.
21. A device, comprising:
a plurality of stacks of nano-structures, wherein the nano-structures each extend in a first horizontal direction, wherein the stacks each extend in a vertical direction and are separated from one another in a second horizontal direction different from the first horizontal direction;
a first gate structure disposed over a first subset of the stacks of nano-structures, wherein the first gate structure circumferentially surrounds each of the nano-structures in the first subset in a cross-sectional side view defined by the vertical direction and the second horizontal direction;
a second gate structure disposed over a second subset of the stacks of nano-structures, wherein the second gate structure circumferentially surrounds each of the nano-structures in the second subset in the cross-sectional side view;
a first conductive layer disposed over a substantial entirety of an upper surface of the first gate structure in the cross-sectional side view;
a second conductive layer disposed over a substantial entirety of an upper surface of the second gate structure in the cross-sectional side view; and
a dielectric structure disposed between the first gate structure and the second gate structure in the second horizontal direction in the cross-sectional side view, wherein the dielectric structure separates the first conductive layer from the second conductive layer.
22. The device of claim 21 , wherein the dielectric structure has slanted side surfaces in the cross-sectional side view.
23. The device of claim 21 , wherein no portion of the first conductive layer or the second conductive layer is disposed directly on an upper surface of the dielectric structure.