IP Library Granted Patent US 12,369,404
Granted Patent B2
US 12,369,404 · App. 17/769,381 · Granted Jul 22, 2025

Electronic circuits and their methods of manufacture

Inventors: Richard Price (Sedgefield, GB); Brian Cobb (Sedgefield, GB)
Assignee: PRAGMATIC SEMICONDUCTOR LIMITED
H10D86/85H01C7/006H10D84/209H10D86/481H10D86/80
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,369,404
App. No.
17/769,381
Granted
Jul 22, 2025
Kind
B2
Abstract

An electronic circuit comprises a first resistor ( 1 ) and a second resistor ( 2 ). The first resistor comprises: a first sheet ( 10 ) of resistive material; and a first pair ( 11, 12 ) of conductive contacts, each arranged in electrical contact with the first sheet, and arranged such that a shortest resistive path in the first sheet between the first pair of contacts passes through the first sheet and has a length equal to a thickness (LI) of the first sheet. The second resistor comprises: a second sheet ( 20 ) of resistive material; and a second pair ( 21, 22 ) of conductive contacts, each arranged in electrical contact with the second sheet, and arranged such that a shortest resistive path (L 2 ) in the second sheet between the second pair of contacts passes along at least a portion of a length of the second sheet.

Claims (44)

1. A thin-film integrated circuit (IC) comprising:

a first resistor, a second resistor, and a substrate arranged to support the first and second resistors, the substrate comprising an electrically insulating layer having a nominal underside and a nominal upper side, the first resistor comprising:

a first sheet of resistive material; and

a first pair of conductive contacts, each arranged in electrical contact with the first sheet, and arranged such that a shortest resistive path in the first sheet between the first pair of contacts passes through the first sheet and has a length equal to a thickness of the first sheet,

and the second resistor comprising:

a second sheet of resistive material; and

a second pair of conductive contacts, each arranged in electrical contact with the second sheet, and arranged such that a shortest resistive path in the second sheet between the second pair of contacts passes along at least a portion of a length of the second sheet,

wherein at least a portion of said second sheet is formed directly on said upper side, and

wherein a first contact of the first pair is formed on said underside, the electrically insulating layer comprises a window extending from the upper side through to the underside and enabling electrical contact of the first sheet to at least a portion of an upper surface of the first contact of the first pair, at least part of the first sheet being formed inside the window and in contact with the first contact, and a second contact of the first pair of contacts being formed at least partially over an upper surface of the first sheet.

2. The thin-film IC in accordance with claim 1 , wherein the first sheet comprises a first quantity of a first resistive material and the second sheet comprises a second quantity of said first resistive material.

3. The thin-film IC in accordance with claim 1 , wherein each of the first and second sheets has the same substantially uniform thickness.

4. The thin-film IC in accordance with claim 1 , wherein the first and second sheets are respective portions of a single sheet formed and then patterned during manufacture of the thin-film IC.

5. The thin-film IC in accordance with claim 1 , wherein a first contact of the first pair is arranged in contact with at least a portion of a first surface of the first sheet, and a second contact of the first pair is arranged in contact with at least a portion of a second surface of the first sheet.

6. The thin-film IC in accordance with claim 1 , wherein the first sheet overlaps at least a portion of the nominal upper side surrounding said window.

7. The thin-film IC in accordance with claim 1 , wherein the second contact of the first pair covers a portion, but not all, of the upper surface of the first sheet.

8. The thin-film IC in accordance with claim 1 , wherein the second contact of the first pair covers the entire upper surface of the first sheet.

9. The thin-film IC in accordance with claim 8 , wherein the second contact of the first pair extends beyond at least one edge of the first sheet so as to cover, and be in direct contact with, at least a portion of said upper side.

10. The thin-film IC in accordance with claim 1 , wherein a first contact of the first pair is formed on said upper side.

11. The thin-film IC in accordance with claim 10 , wherein said first sheet is formed over the first contact of the first pair and covers a portion, but not all, of the first contact of the first pair, or wherein said first sheet is formed over the first contact of the first pair and entirely covers the first contact of the first pair.

12. The thin-film IC in accordance with claim 11 , wherein the first sheet extends beyond at least one edge of the first contact of the first pair so as to cover, and be in direct contact with, a portion of said upper side.

13. The thin-film IC in accordance with claim 11 , wherein a second contact of the first pair is formed over the first sheet so as to cover at least a portion of the first sheet.

14. The thin-film IC in accordance with claim 13 , wherein the second contact of the first pair covers a portion, but not all, of the first sheet, or wherein the second contact of the first pair entirely covers the first sheet.

15. The thin-film IC in accordance with claim 14 , wherein the second contact of the first pair extends beyond at least one edge of the first sheet so as to cover, and be in direct contact with, a portion of said upper side.

16. The thin-film IC in accordance with claim 1 , wherein a first contact of the second pair is formed at least partially over the second sheet so as to cover a first portion of the second sheet, or wherein the first contact of the second pair extends beyond an edge of the second sheet so as to cover, and be in direct contact with, a portion of said upper side.

17. The thin-film IC in accordance with claim 1 , wherein a second contact of the second pair is formed at least partially over the second sheet so as to cover a second portion of the second sheet, optionally wherein the second contact of the second pair extends beyond an edge of the second sheet so as to cover, and be in direct contact with, a portion of said upper side.

18. The thin-film IC in accordance with claim 1 , wherein a first contact of the second pair is formed directly on said upper side.

19. The thin-film IC in accordance with claim 18 , wherein said second sheet is formed over the first contact of the second pair so as to at least partially cover the first contact of the second pair and to cover and be in direct contact with a portion of the upper side adjacent the first contact of the second pair.

20. The thin-film IC in accordance with claim 18 , wherein a second contact of the second pair is formed directly on said upper surface, and said second sheet is formed over the second contact of the second pair so as to at least partially cover the second contact of the second pair.

21. The thin-film IC in accordance with claim 19 , wherein a second contact of the second pair is formed at least partially over the second sheet so as to cover a second portion of the second sheet, optionally wherein the second contact of the second pair extends beyond an edge of the second sheet so as to cover, and be in direct contact with, a portion of said upper side.

22. The thin-film IC in accordance with claim 1 , further comprising at least one of: a transistor; a voltage divider; a biasing network; and an oscillator circuit, and wherein the second resistor is arranged as one of: a load resistor between a terminal of said transistor and a voltage rail; a resistor of the voltage divider or biasing network; and a component of the oscillator circuit.

23. The thin-film IC in accordance with claim 1 , further comprising at least one of: a logic gate; and an oscillator circuit, and the first resistor is arranged as one of: a component of the logic gate; and a component of the oscillator circuit.

24. A method of manufacturing a thin-film integrated circuit (IC) comprising a first resistor, a second resistor, and a substrate arranged to support the first and second resistors, the substrate comprising an electrically insulating layer having a nominal underside and a nominal upper side, the method comprising:

forming a first sheet of resistive material;

forming a first pair of conductive contacts, each arranged in electrical contact with the first sheet, and arranged such that a shortest resistive path in the first sheet between the first pair of contacts passes through the first sheet and has a length equal to a thickness of the first sheet;

forming at least a portion of a second sheet of resistive material directly on said upper side; and

forming a second pair of conductive contacts, each arranged in electrical contact with the second sheet, and arranged such that a shortest resistive path in the second sheet between the second pair of contacts passes along at least a portion of a length of the second sheet, whereby the first sheet and first pair of contacts form the first resistor and the second sheet and second pair of contacts form the second resistor,

wherein the method further comprises:

forming a first contact of the first pair on said underside of the electrically insulating layer;

forming a window extending from the upper side of the electrically insulating layer through to the underside of the electrically insulating layer;

forming a single sheet of resistive material over the first contact of the first pair;

patterning said single sheet to form said first and second sheets, wherein the window enables electrical contact of the first sheet to at least a portion of an upper surface of the first contact of the first pair, at least part of the first sheet being formed inside the window and in contact with the first contact and wherein the first sheet overlaps at least a portion of the nominal upper side of the electrically insulating layer surrounding said window;

forming a single sheet of conductive material over the first and second sheets; and

patterning the single sheet of conductive material to form a second contact of the first pair.

25. The method in accordance with claim 24 , further comprising processing or doping at least a portion of at least one of the first and second sheets to alter its sheet resistance.

Assignments (2)
CHANGE OF NAME Recorded Oct 14, 2024
From: PRAGMATIC PRINTING LIMITED
To: PRAGMATIC SEMICONDUCTOR LIMITED
Reel/Frame 068888/0492 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 11, 2022
From: PRICE, RICHARD; COBB, BRIAN
To: PRAGMATIC PRINTING LTD.
Reel/Frame 059891/0403 →
Priority Claims (1)
GB 1915263 · Oct 22, 2019 · national
Continuity (1)
Related Publication 20230238377A1 · Jul 27, 2023
References Cited (24)
US 4411708A · Winhan · 1983 [cited by applicant]
US 4695853A · Hackleman et al. · 1987 [cited by applicant]
US 6297556B1 · Heger · 2001 [cited by examiner]
US 6542379B1 · Lauffer · 2003 [cited by examiner]
US 20010045618A1 · Trivedi · 2001 [cited by examiner]
US 20020125985A1 · Tsukada · 2002 [cited by examiner]
US 20040201941A1 · Harris et al. · 2004 [cited by applicant]
US 20050000728A1 · Tanaka · 2005 [cited by applicant]
US 20050151127A1 · Iwata et al. · 2005 [cited by applicant]
US 20060174477A1 · Tanaka · 2006 [cited by examiner]
US 20090002120A1 · Molin · 2009 [cited by examiner]
US 20100165525A1 · Fjelstad et al. · 2010 [cited by applicant]
US 20190139754A1 · Hsueh et al. · 2019 [cited by applicant]
US 20200203536A1 · Karino · 2020 [cited by examiner]
US 20200395151A1 · Karino · 2020 [cited by examiner]
EP 1494514A2 · 2005 [cited by applicant]
JP 2005116773A · 2005 [cited by applicant]
Invitation to Pay Additional Fees and, Where Applicable, Protest Fee for International Application No. PCT/GB2020/052672, mailed Jan. 25, 2021. [cited by applicant]
International Search Report for International Application No. PCT/GB2020/052672, mailed Mar. 18, 2021. [cited by applicant]
Written Opinion for International Application No. PCT/GB2020/052672, mailed Mar. 18, 2021. [cited by applicant]
Combined Search and Examination Report Under Sections 17 and 18(3) for Great Britain Application No. 1915263.6, mailed Apr. 15, 2020. [cited by applicant]
Examination Report Under Section 18(3) for Great Britain Application No. 1915263.6, mailed Feb. 1, 2022. [cited by applicant]
Examination Report Under Section 18(3) for Great Britain Application No. 1915263.6, mailed Aug. 16, 2022. [cited by applicant]
International Preliminary Report on Patentability for International Application No. PCT/GB2020/052672, mailed May 5, 2022. [cited by applicant]