IP Library Granted Patent US 12,433,019
Granted Patent B2
US 12,433,019 · App. 17/770,360 · Granted Sep 30, 2025

Semiconductor device

Inventors: Takahiko Ishizu (Kanagawa, JP); Takayuki Ikeda (Kanagawa, JP); Atsushi Miyaguchi (Kanagawa, JP); Shunpei Yamazaki (Tokyo, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H10D84/856H01L21/02565H10D30/6734H10D30/6755H10D84/08H10D99/00
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Quick Facts
Patent No.
US 12,433,019
App. No.
17/770,360
Granted
Sep 30, 2025
Kind
B2
Abstract

A semiconductor device having a novel structure is provided. The semiconductor device includes a p-channel transistor and an n-channel transistor provided over a silicon substrate. One of a source and a drain of the p-channel transistor is electrically connected to a first power supply line, one of a source and a drain of the n-channel transistor is electrically connected to a second power supply line, and the other of the source and the drain of the p-channel transistor is connected to the other of the source and the drain of the n-channel transistor. The p-channel transistor includes a first gate electrode and a first back gate electrode provided to face the first gate electrode with a first channel formation region therebetween. The first back gate electrode is formed using a region where an impurity element imparting conductivity is selectively introduced to the silicon substrate. The n-channel transistor is provided above a layer including the p-channel transistor.

Claims (13)

1. A semiconductor device comprising:

a p-channel transistor and a first n-channel transistor provided over a silicon substrate,

wherein one of a source and a drain of the p-channel transistor is electrically connected to a first power supply line, one of a source and a drain of the first n-channel transistor is electrically connected to a second power supply line, and the other of the source and the drain of the p-channel transistor is electrically connected to the other of the source and the drain of the first n-channel transistor,

wherein the p-channel transistor comprises a first gate electrode and a first back gate electrode provided to face the first gate electrode with a first channel formation region therebetween,

wherein the first back gate electrode is electrically connected to one of a source and a drain of a second n-channel transistor,

wherein the second n-channel transistor comprises a semiconductor layer including a metal oxide,

wherein the first back gate electrode is formed using a region where an impurity element imparting conductivity is selectively introduced to the silicon substrate,

wherein the first n-channel transistor comprises a second gate electrode and a second back gate electrode provided to face the second gate electrode with a second channel formation region therebetween,

wherein the first n-channel transistor is provided above a layer comprising the p-channel transistor, and

wherein a potential supplied to the first back gate electrode is different from a potential supplied to the second back gate electrode.

2. The semiconductor device according to claim 1 , wherein the second channel formation region comprises a metal oxide.

3. The semiconductor device according to claim 2 , wherein the metal oxide comprises In, Ga, and Zn.

4. The semiconductor device according to claim 1 , wherein a potential supplied to the first back gate electrode is higher than a potential supplied to the second back gate electrode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 20, 2022
From: ISHIZU, TAKAHIKO; IKEDA, TAKAYUKI; MIYAGUCHI, ATSUSHI; YAMAZAKI, SHUNPEI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 059647/0737 →
Priority Claims (1)
JP 2019-199663 · Nov 1, 2019 · national
Continuity (1)
Related Publication 20220384433A1 · Dec 1, 2022
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