Row and column decoders comprising fully depleted silicon-on-insulator transistors for use in flash memory systems
The present invention relates to a flash memory system wherein one or more circuit blocks utilize fully depleted silicon-on-insulator transistor design to minimize leakage.
1. A flash memory system comprising:
an array of flash memory cells arranges into rows and columns; and
a row decoder for selecting a row of flash memory cells in the array for a read or program operation, the row decoder comprising one or more fully depleted silicon-on-insulator NMOS transistors and one or more fully depleted silicon-on-insulator PMOS transistors;
wherein each of the one or more fully depleted silicon-on-insulator NMOS transistors comprises an n-well under a buried oxide layer and coupled to a first dynamic voltage source that provides a forward body bias or a reverse body bias to the NMOS transistor; and
wherein each of the one or more fully depleted silicon-on-insulator PMOS transistors comprises a p-well under a buried oxide layer and coupled to a second dynamic voltage source that provides a forward body bias or a reverse body bias to the PMOS transistor.
2. The flash memory system of claim 1 , wherein the flash memory cells comprise source side injection flash memory cells.
3. The flash memory system of claim 2 , wherein each source side injection flash memory cell comprises:
an erase gate to provide erasing;
a coupling gate; and
a source line to provide programming current.
4. The flash memory system of claim 1 , wherein the row decoder comprises:
a row driver comprising a PMOS transistor comprising a p-well underneath a channel and coupled to the first dynamic voltage source that provides a forward body bias or a reverse body bias to the PMOS transistor and an NMOS transistor with an n-well underneath a channel and coupled to the second dynamic voltage source that provides a forward body bias or a reverse body bias to the NMOS transistor.
5. The flash memory system of claim 4 wherein the row decoder further comprises:
a row pre-driver comprising a PMOS transistor comprising a p-well underneath a channel and a NMOS transistor comprising an n-well underneath a channel.
6. The flash memory system of claim 5 , wherein the row pre-driver further comprises a decoding PMOS transistor with a p-well underneath a channel.
7. The flash memory system of claim 1 wherein the row decoder further comprises a NAND gate and an INVERTER gate comprising a PMOS transistor comprising a p-well underneath a channel and an NMOS transistor comprising an n-well underneath channel.
8. A flash memory system comprising:
an array of flash memory cells arranges into rows and columns; and
a row decoder for selecting a row of flash memory cells in the array for a read or write operation, the row decoder comprising one or more fully depleted silicon-on-insulator NMOS transistors and one or more fully depleted silicon-on-insulator PMOS transistors;
wherein the row decoder comprises:
one or more fully depleted silicon-on-insulator NMOS transistors comprising a p-well under a buried oxide layer and coupled to a first dynamic voltage source that provides a forward body bias or a reverse body bias to the NMOS transistor; and
one or more fully depleted silicon-on-insulator PMOS transistors comprising an n-well under a buried oxide layer and coupled to a second dynamic voltage source that provides a forward body bias or a reverse body bias to the PMOS transistor.
9. The flash memory system of claim 8 , wherein the row decoder comprises:
a row driver comprising a PMOS transistor and an NMOS transistor comprising an n-well underneath a channel.
10. The flash memory system of claim 9 , wherein the row decoder further comprises: a row pre-driver comprising a row address decoder comprising a NAND gate comprising a p-well underneath a channel and an INVERTER gate comprising an n-well underneath a channel.
11. The flash memory system of claim 9 , wherein the row decoder further comprises a row pre-driver comprising a PMOS transistor and an NMOS transistor comprising a p-well underneath a channel.
12. The flash memory system of claim 9 , wherein the row pre-driver further comprises a decoding PMOS transistor with an n-well underneath a channel.
13. The flash memory system of claim 9 wherein the row pre-driver further comprises a row address decoder comprising a NAND gate with p-well underneath a channel and an INVERTER gate comprising an n-well underneath a channel.
14. A flash memory system comprising:
an array of flash memory cells arranges into rows and columns; and
a column decoder for selecting a column of flash memory cells in the array for a read or write operation, the column decoder comprising:
a plurality of fully depleted silicon-on-insulator NMOS transistors each comprising a p-well under a buried oxide layer for column de-selection and coupled to a first dynamic voltage source that provides a forward body bias or a reverse body bias to the NMOS transistor; and
a plurality of fully depleted silicon-on-insulator NMOS transistors each comprising an n-well under a buried oxide layer for column selection and coupled to a second dynamic voltage source that provides a forward body bias or a reverse body bias to the NMOS transistor.
15. The flash memory system of claim 14 , wherein the memory cells comprise source side injection flash memory cells, each comprising:
an erase gate to provide erasing;
a coupling gate; and
a source line to provide programming current.