Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device
A silicon carbide semiconductor device includes a silicon carbide substrate, a first electrode, and a second electrode. The silicon carbide substrate has a first main surface, a second main surface, a first impurity region, a second impurity region, and a third impurity region. The first electrode is in contact with each of the second impurity region and the third impurity region on the first main surface. The second electrode is in contact with the first impurity region on the second main surface. The second impurity region includes a first region and a second region disposed between the first region and the second main surface and in contact with the first region. An impurity concentration of the first region is more than or equal to 6×10 16 cm −3 .
1. A silicon carbide semiconductor device comprising:
a silicon carbide substrate having a first main surface, a second main surface, a first impurity region, a second impurity region, and a third impurity region, the second main surface being opposite to the first main surface, the first impurity region constituting at least a portion of the second main surface, the first impurity region having a first conductivity type, the second impurity region constituting at least a portion of the first main surface, the second impurity region being provided in contact with the first impurity region, the second impurity region having a second conductivity type different from the first conductivity type, the third impurity region being provided in contact with the second impurity region so as to be separated from the first impurity region, the third impurity region having the first conductivity type;
a first electrode in contact with each of the second impurity region and the third impurity region on the first main surface;
a gate electrode; and
a second electrode in contact with the first impurity region on the second main surface, wherein
the second impurity region includes a first region and a second region disposed between the first region and the second main surface and in contact with the first region,
an impurity concentration of the first region is more than or equal to 6×10 16 cm −3 ,
when a drain current density is measured while changing a drain voltage under a temperature condition of 25° C. to 175° C., an inclination of the drain current density with respect to the drain voltage becomes smaller as a temperature is increased, and
the second region having a super junction region formed to face the gate electrode.
2. The silicon carbide semiconductor device according to claim 1 , wherein an impurity concentration of the second region is more than or equal to 6×10 16 cm −3 .
3. The silicon carbide semiconductor device according to claim 1 , wherein the silicon carbide semiconductor device is a planar type.
4. The silicon carbide semiconductor device according to claim 1 , wherein
a trench is provided in the silicon carbide substrate, and
the trench has a side surface in contact with each of the first impurity region, the second impurity region, and the third impurity region, and a bottom surface contiguous to the side surface and in contact with the first impurity region.
5. The silicon carbide semiconductor device according to claim 4 , wherein in a cross section perpendicular to the first main surface, the trench has a U-shape.
6. The silicon carbide semiconductor device according to claim 4 , wherein in a cross section perpendicular to the first main surface, the trench has a V-shape.
7. The silicon carbide semiconductor device according to claim 1 , wherein the first main surface is a (000-1) plane or a plane inclined at an angle of less than or equal to 8° with respect to the (000-1) plane.
8. The silicon carbide semiconductor device according to claim 1 , wherein the impurity concentration of the first region is more than an impurity concentration of the second region.
9. The silicon carbide semiconductor device according to claim 8 , wherein the impurity concentration of the first region is less than or equal to 1×10 19 cm −3 .
10. The silicon carbide semiconductor device according to claim 1 , wherein when the temperature is increased from 25° C. to 175° C., an amount of change of the inclination of the drain current density with respect to the drain voltage is less than or equal to 20 A/(cm 2 ×V).
11. The silicon carbide semiconductor device according to claim 1 , wherein the second region has a joint region disposed on the super junction region, and in a short-side direction of the super junction region, a maximum width of the joint region is larger than a width of the super junction region.
12. The silicon carbide semiconductor device according to claim 1 , wherein
the super junction region has a first doped region and a second doped region each having the second conductivity type, and
the first doped region is formed to face the gate electrode and the second doped region is formed not to face the gate electrode.
13. A silicon carbide semiconductor device comprising:
a silicon carbide substrate having a first main surface, a second main surface, a first impurity region, a second impurity region, and a third impurity region, the second main surface being opposite to the first main surface, the first impurity region constituting at least a portion of the second main surface, the first impurity region having a first conductivity type, the second impurity region constituting at least a portion of the first main surface, the second impurity region being provided in contact with the first impurity region, the second impurity region having a second conductivity type different from the first conductivity type, the third impurity region being provided in contact with the second impurity region so as to be separated from the first impurity region, the third impurity region having the first conductivity type;
a first electrode in contact with each of the second impurity region and the third impurity region on the first main surface;
a gate electrode; and
a second electrode in contact with the first impurity region on the second main surface, wherein
the second impurity region includes a first region and a second region disposed between the first region and the second main surface and in contact with the first region,
a point defect density of the first region is more than or equal to 6×10 12 cm −3 ,
when a drain current density is measured while changing a drain voltage under a temperature condition of 25° C. to 175° C., an inclination of the drain current density with respect to the drain voltage becomes smaller as a temperature is increased, and
the second region has a super junction region formed to face the gate electrode.
14. The silicon carbide semiconductor device according to claim 13 , wherein the point defect density of the first region is less than or equal to 1×10 14 cm −3 .
15. The silicon carbide semiconductor device according to claim 13 , wherein the silicon carbide semiconductor device is a planar type.
16. The silicon carbide semiconductor device according to claim 13 , wherein
a trench is provided in the silicon carbide substrate, and
the trench has a side surface in contact with each of the first impurity region, the second impurity region, and the third impurity region, and a bottom surface contiguous to the side surface and in contact with the first impurity region.
17. The silicon carbide semiconductor device according to claim 16 , wherein in a cross section perpendicular to the first main surface, the trench has a U-shape.
18. The silicon carbide semiconductor device according to claim 16 , wherein in a cross section perpendicular to the first main surface, the trench has a V-shape.
19. The silicon carbide semiconductor device according to claim 13 , wherein the first main surface is a (000-1) plane or a plane inclined at an angle of less than or equal to 8° with respect to the (000-1) plane.
20. The silicon carbide semiconductor device according to claim 13 , wherein the impurity concentration of the first region is more than an impurity concentration of the second region.
21. The silicon carbide semiconductor device according to claim 20 , wherein the impurity concentration of the first region is less than or equal to 1×10 19 cm −3 .
22. The silicon carbide semiconductor device according to claim 13 , wherein when the temperature is increased from 25° C. to 175° C., an amount of change of the inclination of the drain current density with respect to the drain voltage is less than or equal to 20 A/(cm 2 ×V).
23. A method of manufacturing a silicon carbide semiconductor device, the method comprising:
preparing a silicon carbide substrate having a first main surface, a second main surface, a first impurity region, a second impurity region, and a third impurity region, the second main surface being opposite to the first main surface, the first impurity region constituting at least a portion of the second main surface, the first impurity region having a first conductivity type, the second impurity region constituting at least a portion of the first main surface, the second impurity region being provided in contact with the first impurity region, the second impurity region having a second conductivity type different from the first conductivity type, the third impurity region being provided in contact with the second impurity region so as to be separated from the first impurity region, the third impurity region having the first conductivity type;
forming a first electrode in contact with each of the second impurity region and the third impurity region on the first main surface;
forming a gate electrode; and
forming a second electrode in contact with the first impurity region on the second main surface, wherein
the second impurity region includes a first region and a second region disposed between the first region and the second main surface and in contact with the first region,
an impurity concentration of the first region is more than or equal to 6×10 16 cm −3 ,
the first region is formed by ion implantation,
when a drain current density is measured while changing a drain voltage under a temperature condition of 25° C. to 175° C., an inclination of the drain current density with respect to the drain voltage becomes smaller as a temperature is increased, and
the second region has a super junction formed to face the gate electrode.
24. The method of manufacturing the silicon carbide semiconductor device according to claim 23 , wherein the second region is formed by ion implantation.
25. The method of manufacturing the silicon carbide semiconductor device according to claim 23 , wherein the first impurity region is formed by epitaxial growth under a temperature condition of more than or equal to 1500° C. and less than or equal to 1750° C.
26. The method of manufacturing the silicon carbide semiconductor device according to claim 23 , wherein
the preparing of the silicon carbide substrate includes performing activation annealing, and
the performing of the activation annealing is performed under a temperature condition of more than or equal to 1600° C. and less than or equal to 1850° C.
27. The silicon carbide semiconductor device according to claim 23 , wherein when the temperature is increased from 25° C. to 175° C., an amount of change of the inclination of the drain current density with respect to the drain voltage is less than or equal to 20 A/(cm 2 ×V).