IP Library Granted Patent US 12,400,941
Granted Patent B2
US 12,400,941 · App. 17/805,096 · Granted Aug 26, 2025

Semiconductor device and method of disposing electrical components over side surfaces of interconnect substrate

Inventors: GunHyuck Lee (Incheon, KR); HeeSoo Lee (Incheon, KR); SangHyun Son (Seoul, KR); Bokyeong Hwang (Incheon, KR)
Assignee: STATS ChipPAC Pte. Ltd.
H01L23/49805H01L21/4853H01L21/4857H01L21/565H01L23/3121H01L23/49822H01L23/49838H01L23/552
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Quick Facts
Patent No.
US 12,400,941
App. No.
17/805,096
Granted
Aug 26, 2025
Kind
B2
Abstract

A semiconductor device has an interconnect substrate with a conductive via. A first electrical component is disposed over a major surface of the interconnect substrate. An electrical interconnect compound is disposed over the conductive via exposed from a side surface of the interconnect substrate. The electrical interconnect compound can be applied with a tilt nozzle oriented at an angle. A second electrical component is disposed on the electrical interconnect compound on the conductive via exposed from the side surface of the interconnect substrate. A plurality of second electrical components can be disposed on two or more side surfaces of the interconnect substrate. The interconnect substrate can have a plurality of stacked conductive vias and the second electrical component is disposed over the stacked conductive vias. An encapsulant is deposited over the first electrical component and interconnect substrate. A shielding layer can be formed over the encapsulant.

Claims (48)

1. A semiconductor device, comprising:

an interconnect substrate including a conductive layer internal to the interconnect substrate, wherein the conductive layer includes a first conductive via exposed from a side surface of the interconnect substrate;

a first electrical component disposed over a major surface of the interconnect substrate; and

a second electrical component disposed in contact with the first conductive via on the side surface of the interconnect substrate.

2. The semiconductor device of claim 1 , further including an electrical interconnect compound disposed over the first conductive via exposed from the side surface of the interconnect substrate.

3. The semiconductor device of claim 1 , further including a plurality of second electrical components disposed on two or more side surfaces of the interconnect substrate.

4. The semiconductor device of claim 1 , wherein the first conductive via includes a plurality of stacked conductive vias and the second electrical component is disposed in contact with the stacked conductive vias.

5. The semiconductor device of claim 1 , further including an encapsulant deposited over the first electrical component and interconnect substrate.

6. The semiconductor device of claim 5 , further including a shielding layer formed over the encapsulant.

7. The semiconductor device of claim 1 , wherein the first conductive via extends from a first surface of the interconnect substrate to a second surface of the interconnect substrate opposite the first surface of the interconnect substrate.

8. The semiconductor device of claim 1 , wherein the conductive layer further includes a second conductive via vertically and laterally offset from the first conductive via.

9. A semiconductor device, comprising:

a substrate including a first conductive via exposed from a side surface of the substrate and a second conductive via exposed from the side surface of the substrate;

a first electrical component disposed over a major surface of the substrate; and

a second electrical component disposed over the first conductive via and second conductive via on the side surface of the substrate.

10. The semiconductor device of claim 9 , further including an electrical interconnect compound disposed over the side surface of the substrate.

11. The semiconductor device of claim 9 , further including a plurality of second electrical components disposed over two or more side surfaces of the substrate.

12. The semiconductor device of claim 9 , wherein providing the substrate includes:

forming a conductive layer internal to the substrate, wherein the the first conductive via is part of the conductive layer; and

disposing the second electrical component is disposed over the first conductive via.

13. The semiconductor device of claim 9 , wherein the substrate includes a plurality of stacked conductive vias and the second electrical component is disposed over the stacked conductive vias.

14. The semiconductor device of claim 9 , further including an encapsulant deposited over the first electrical component and substrate.

15. The semiconductor device of claim 14 , further including a shielding layer formed over the encapsulant.

16. The semiconductor device of claim 9 , wherein the first conductive via extends from a first surface of the substrate to a second surface of the substrate opposite the first surface of the substrate.

17. The semiconductor device of claim 9 , wherein the substrate includes a second conductive via vertically and laterally offset from the first conductive via.

18. A method of making a semiconductor device, comprising:

providing an interconnect substrate including a conductive layer internal to the interconnect substrate, wherein the conductive layer includes a first conductive via exposed from a side surface of the interconnect substrate;

disposing a first electrical component over a major surface of the interconnect substrate; and

disposing a second electrical component over the first conductive via exposed from a side surface of the interconnect substrate.

19. The method of claim 18 , further including disposing an electrical interconnect compound over the first conductive via exposed from the side surface of the interconnect substrate.

20. The method of claim 18 , further including disposing a plurality of second electrical components over two or more side surfaces of the interconnect substrate.

21. The method of claim 18 , wherein providing the interconnect substrate includes:

forming a plurality of stacked conductive vias through the interconnect substrate; and

disposing the second electrical component over the stacked conductive vias.

22. The method of claim 18 , further including depositing an encapsulant over the first electrical component and interconnect substrate.

23. The method of claim 22 , further including forming a shielding layer over the encapsulant.

24. The method of claim 18 , wherein the first conductive via extends from a first surface of the interconnect substrate to a second surface of the interconnect substrate opposite the first surface of the interconnect substrate.

25. The method of claim 18 , wherein the conductive layer further includes a second conductive via vertically and laterally offset from the first conductive via.

26. A method of making a semiconductor device, comprising:

providing a substrate including a first conductive via exposed from a side surface of the substrate and a second conductive via exposed from the side surface of the substrate;

disposing a first electrical component over a major surface of the substrate; and

disposing a second electrical component over the first conductive via and second conductive via on the side surface of the substrate.

27. The method of claim 26 , further including disposing an electrical interconnect compound over the side surface of the substrate.

28. The method of claim 26 , further including disposing a plurality of second electrical components over two or more side surfaces of the substrate.

29. The method of claim 26 , further including depositing an encapsulant over the first electrical component and substrate.

30. The method of claim 29 , further including forming a shielding layer over the encapsulant.

31. The method of claim 26 , wherein the first conductive via extends from a first surface of the substrate to a second surface of the substrate opposite the first surface of the substrate.

32. The method of claim 26 , wherein the substrate includes a second conductive via vertically and laterally offset from the first conductive via.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 2, 2022
From: LEE, GUNHYUCK; LEE, HEESOO; SON, SANGHYUN; HWANG, BOKYEONG
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 060086/0121 →
Continuity (1)
Related Publication 20230395477A1 · Dec 7, 2023
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