Hybrid signal and power track for stacked transistors
Provided is a semiconductor device. The semiconductor device comprises a first transistor stacked above a second transistor. The semiconductor device further includes a frontside power rail that is electrically coupled to a source/drain epitaxy of the first transistor. The semiconductor device further includes a backside power rail that is electrically coupled to a source/drain epitaxy of the second transistor. The semiconductor device further includes a plurality of frontside signal lines. The plurality of signal lines includes a first frontside signal line that is electrically coupled to a source/drain epitaxy of the second transistor. The frontside signal line is connected to the source/drain epitaxy through a backside contact and an interlevel via.
1 . A semiconductor device comprising:
a first transistor stacked on top of a second transistor;
a frontside power rail that is electrically coupled to a source/drain epitaxy of the first transistor;
a backside power rail that is electrically coupled to a source/drain epitaxy of the second transistor; and
a plurality of frontside signal lines, wherein a first frontside signal line is electrically coupled to the source/drain epitaxy of the second transistor through a backside contact and an interlevel via, wherein the interlevel via is located between cell boundaries of horizontally adjacent transistors.
2 . The semiconductor device of claim 1 , further comprising:
a middle-of-line structure (MOL); and
one or more MOL contacts,
wherein the interlevel via and the one or more MOL contacts have approximately a same taper angles.
3 . The semiconductor device of claim 1 , wherein the first frontside signal line is connected to the source/drain epitaxy of the second transistor through a frontside via that connects the first frontside signal line to the interlevel via.
4 . The semiconductor device of claim 1 , further comprising:
a second frontside signal line that is connected to a source/drain epitaxy of the first transistor through a frontside contact and frontside via.
5 . The semiconductor device of claim 1 , wherein the frontside power rail is connected to the source/drain epitaxy of the first transistor through a frontside via.
6 . The semiconductor device of claim 1 , wherein the backside power rail is connected to the source/drain epitaxy of the second transistor through a backside via.
7 . The semiconductor device of claim 5 , wherein first and second transistors are connected to create a complementary metal-oxide semiconductor (CMOS) cell.
8 . The semiconductor device of claim 6 , wherein the first and second transistors form a complementary field-effect transistor (CFET).
9 . The semiconductor device of claim 1 , further comprising a backside power distribution network (BSPDN) connected to the backside power rail opposite the first and second transistors.
10 . The semiconductor device of claim 1 , wherein the first and second transistors are nanosheet transistors.
11 . A semiconductor device comprising:
a stacked transistor comprising:
a bottom transistor having one or more bottom source/drain epitaxy regions; and
a top transistor having one or more top source/drain epitaxy regions; and
a plurality of frontside signal lines,
wherein a bottom source/drain epitaxy region is connected to a first frontside signal line though an interlevel via that is located between cell boundaries of the stacked transistor and an adjacent device.
12 . The semiconductor device of claim 11 , wherein the interlevel via is connected to the bottom source/drain epitaxy region through a backside contact.
13 . The semiconductor device of claim 12 , wherein the interlevel via is connected to the first signal line through a frontside via.
14 . The semiconductor device of claim 12 , wherein a top source/drain epitaxy region is connected to a second frontside signal line though a second frontside via.
15 . The semiconductor device of claim 11 , further comprising:
a backside power distribution network (BSPDN) located below the bottom transistor; and
a backside power rail electrically connected to the BSPDN, the backside power rail being located between the BSPDN and the bottom transistor,
wherein a bottom source/drain epitaxy region of the bottom transistor is connected to the backside power rail through a backside via and a backside contact, the backside contact connecting the backside via to the backside power rail.
16 . A method for fabricating a semiconductor device, the method comprising:
forming a stacked FET, the stacked FET including a top transistor with at least two top source/drain epitaxies and a bottom transistor with at least two bottom source/drain epitaxies;
forming one or more middle-of-line (MOL) structures;
forming one or more frontside contacts and frontside vias to wire a first top source/drain epitaxy to a frontside power rail and a second top source/drain epitaxy to a signal line;
forming one or more BEOL layers; and
forming one or more backside contacts below the bottom source/drain epitaxies, wherein:
at least one backside contact connects a bottom source/drain epitaxy to a first MOL structure, and
at least one backside contact connects a bottom source/drain epitaxy to a backside power rail through a backside via wherein the first MOL structure includes an interlevel via that is formed lateral to the stacked FET.
17 . The method of claim 16 , further comprising, after forming the one or more BEOL layers and before forming the one or more backside contacts:
bonding a carrier wafer to the one or more BEOL layers;
flipping the semiconductor device; and
removing a substrate from the semiconductor device.
18 . The method of claim 17 , wherein removing the substrate comprises:
removing a first portion of the substrate, selective to an embedded etch stop layer;
removing the etch stop layer; and
removing a second portion of the substrate.