Uniform trenches in semiconductor devices and manufacturing method thereof
View Patent ↗The present disclosure describes a semiconductor device having radiation-sensing regions separated by trench isolation structures. The semiconductor structure includes a first trench fill structure on a substrate and a second trench fill structure on the substrate. The first trench fill structure has a first width and a convex bottom surface. The second trench fill structure has a concave bottom surface and a second width greater than the first width.
1 . A semiconductor structure, comprising:
a first trench fill structure on a substrate, wherein the first trench fill structure has a first width and a convex bottom surface; and
a second trench fill structure on the substrate and intersecting with the first trench fill structure, wherein:
the second trench fill structure has a concave bottom surface; and
the second trench fill structure has a second width greater than the first width.
2 . The semiconductor structure of claim 1 , wherein the first trench fill structure has a first depth and the second trench fill structure has a second depth, and wherein a ratio of a difference between the first and second depths to the first depth is less than about 20%.
3 . The semiconductor structure of claim 1 , wherein the second trench fill structure further comprises a protrusion and a recess at the concave bottom surface, and wherein a distance between the protrusion and the recess ranges from about 10 Å to about 2000 Å.
4 . The semiconductor structure of claim 3 , wherein a ratio of the distance to a depth of the first trench fill structure ranges from about 0.02% to about 5%.
5 . The semiconductor structure of claim 1 , wherein the first trench fill structure has a depth, and wherein a ratio of the depth to the first width ranges from about 20 to about 100.
6 . The semiconductor structure of claim 5 , wherein the depth ranges from about 2 μm to about 4 μm.
7 . The semiconductor structure of claim 1 , wherein the second trench fill structure has a depth, and wherein a ratio of the depth to the second width ranges from about 5 to about 50.
8 . The semiconductor structure of claim 1 , wherein a ratio of the second width to the first width ranges from about 2 to about 100.
9 . The semiconductor structure of claim 1 , wherein the first width ranges from about 40 nm to about 100 nm and the second width ranges from about 80 nm to about 400 nm.
10 . A semiconductor device, comprising:
a first chip, wherein the first chip comprises:
a plurality of pixels on a first side of the first chip; and
first and second trench fill structures isolating the plurality of pixels from one another, wherein:
the first and second trench fill structures have a substantially same depth;
the first and second trench fill structures have different widths;
the first trench fill structure has a convex bottom surface;
the second trench fill structure is in contact with the first trench fill structure; and
the second trench fill structure has a concave bottom surface; and
a second chip bonded to a second side of the first chip, wherein the second side is opposite to the first side.
11 . The semiconductor device of claim 10 , wherein the first trench fill structure has a first depth and the second trench fill structure has a second depth, and wherein a ratio of a difference between the first and second depths to the first depth is less than about 20%.
12 . The semiconductor device of claim 10 , wherein the second trench fill structure comprises a protrusion and a recess at the concave bottom surface, and wherein a ratio of a distance between the protrusion and the recess to a depth of the first trench fill structure ranges from about 0.02% to about 5%.
13 . The semiconductor device of claim 10 , wherein the first trench fill structure has a first width and the second trench fill structure has a second width, and wherein a ratio of the second width to the first width ranges from about 2 to about 100.
14 . A method, comprising:
forming, on a substrate, a first pattern having a first width and a second pattern having a second width greater than the first width;
forming, within the second pattern, a third pattern having a third width less than the second width; and
forming, on the substrate, a first trench under the first pattern and a second trench under the second and third patterns.
15 . The method of claim 14 , wherein forming the first pattern and the second pattern comprises:
depositing a mask layer on the substrate; and
etching the mask layer into the first and second patterns.
16 . The method of claim 14 , wherein forming the third pattern comprises:
depositing a dielectric material on the first and second patterns;
forming a mask structure on the dielectric material above the second pattern; and
etching the dielectric material and the mask structure.
17 . The method of claim 14 , wherein forming the first pattern and the second pattern comprises:
depositing a first etch stop layer on the substrate;
depositing a mask layer on the first etch stop layer;
depositing a second etch stop layer on the mask layer; and
etching the mask layer and the second etch stop layer.
18 . The method of claim 17 , wherein forming the third pattern comprises:
depositing a dielectric material on the first and second patterns to fill the first pattern;
depositing a coating layer on the dielectric material to fill the second pattern;
etching the coating layer and the dielectric material to form a mask structure in the second pattern; and
removing the first etch stop layer exposed by the first pattern, the mask structure, and the second pattern.
19 . The method of claim 14 , wherein forming the first trench and the second trench comprises etching the substrate having the first, second, and third patterns with a fluorine-based plasma.
20 . The method of claim 14 , further comprising filling the first and second trenches with a dielectric material.