Gate structures for tuning threshold voltage
View Patent ↗A semiconductor device includes a first gate structure that includes a first interfacial layer, a first gate dielectric layer disposed over the first interfacial layer, and a first gate electrode disposed over the first gate dielectric layer. The semiconductor device also includes a second gate structure that includes a second interfacial layer, a second gate dielectric layer disposed over the second interfacial layer, and a second gate electrode disposed over the second gate dielectric layer. The first interfacial layer contains a different amount of a dipole material than the second interfacial layer.
1. A method, comprising:
forming a mask layer directly on a first interfacial layer (IL) for a first gate structure and directly on a second IL for a second gate structure;
patterning the mask layer to remove a portion of the mask layer formed over the first IL;
forming a dipole layer, wherein a first portion of the dipole layer is formed directly on the first IL, and wherein a second portion of the dipole layer is formed on a remaining portion of the mask layer disposed over the second IL;
performing a dipole drive-in process to drive a material of the dipole layer into the first IL and into the second IL
removing the dipole layer and removing the remaining portion of the mask layer after the dipole drive-in process has been performed;
forming a gate dielectric layer directly on the first IL and on the second IL;
forming one or more work function metal layers over the gate dielectric layer; and
forming a fill metal over the one or more work function metal layers.
2. The method of claim 1 , wherein:
the dipole drive-in process forms a first dipole-penetrated portion in the first IL and a second dipole-penetrated portion in the second IL;
the first dipole-penetrated portion has a first depth;
the second dipole-penetrated portion has a second depth; and
the first depth is greater than the second depth.
3. The method of claim 1 , wherein after the dipole drive-in process has been performed:
the first IL has a first concentration level of the material of the dipole layer;
the second IL has a second concentration level of the material of the dipole layer; and
the first concentration level is greater than the second concentration level.
4. The method of claim 1 , wherein the dipole drive-in process comprises an annealing process performed in a temperature range between about 600 degrees Celsius and 800 degrees Celsius and with a nitrogen gas.
5. The method of claim 1 , wherein the forming the one or more work function metal layers comprises:
forming a first work function metal layer over the gate dielectric layer;
forming a second work function metal layer over the first work function metal layer; and
forming a third work function metal layer over the second work function metal layer;
wherein:
the first work function metal layer and the third work function metal layer have same material compositions; and
the second work function metal layer has a different material composition than the first work function metal layer and the third work function metal layer.
6. The method of claim 5 , wherein the first work function metal layer, the second work function metal layer, and the third work function metal layer are formed in-situ using a same deposition tool.
7. The method of claim 1 , wherein the forming the dipole layer comprises depositing a metal oxide material as the dipole layer.
8. The method of claim 7 , wherein the depositing the metal oxide material comprises depositing lanthanum oxide, yttrium oxide, magnesium oxide, or strontium oxide as the metal oxide material.
9. The method of claim 1 , wherein the forming the dipole layer comprises performing an atomic layer deposition process that uses at least La(fAMD) 3 or La(thd) 3 as precursors.
10. The method of claim 1 , wherein the first gate structure has a lower threshold voltage than the second gate structure.
11. A method, comprising:
forming a mask layer over a first interfacial layer (IL) for a first gate structure and over a second IL for a second gate structure;
etching away a first portion of the mask layer over the first IL while leaving a second portion of the mask layer over the second IL substantially intact;
depositing a dipole layer over the first IL and over the second portion of the mask layer, wherein the dipole layer contains a metal oxide material;
performing an annealing process, the annealing process facilitating a penetration of the metal oxide material of the dipole layer into the first IL and into the second IL, wherein a depth or a concentration of the metal oxide material in the first IL exceeds a depth or a concentration of the metal oxide material in the second IL after the annealing process has been performed;
removing the dipole layer and the second portion of the mask layer after the annealing process has been performed;
after the removing, forming a first gate dielectric layer over the first IL and forming a second gate dielectric layer over the second IL; and
forming a rest of the first gate structure over the first gate dielectric layer and a rest of the second gate structure over the second gate dielectric layer.
12. The method of claim 11 , wherein:
the annealing process is performed in a temperature range between about 600 degrees Celsius and 800 degrees Celsius and with a nitrogen gas; and
the metal oxide material includes lanthanum oxide, yttrium oxide, magnesium oxide, or strontium oxide.
13. The method of claim 11 , wherein the mask layer is formed such that a bottommost surface of the mask layer extends to a topmost surface of the first IL and to a topmost surface of the second IL.
14. A method, comprising:
forming a first mask over a first interfacial layer (IL), a second IL, and a third IL, wherein the first IL, the second IL, and the third IL are components of a first gate, a second gate, and a third gate, respectively;
removing the first mask from the first gate and the second gate but not from the third gate;
forming a second mask over the first IL, over the second IL, and over a remaining portion of the first mask over the third IL;
removing the second mask from the first gate but not from the second gate and the third gate;
depositing a dipole layer over the first IL and over remaining portions of the second mask over the second gate and the third gate;
causing a material of the dipole layer to penetrate into the first IL, into the second IL, and into the third IL; and
after the material of the dipole layer has penetrated into the first IL, into the second IL, and into the third IL, forming a first gate dielectric of the first gate over the first IL, forming a second gate dielectric of the second gate over the second IL, and forming a third gate dielectric of the third gate over the third IL.
15. The method of claim 14 , wherein the causing comprises performing a thermal process with a temperature between about 600 degrees Celsius and about 800 degrees Celsius.
16. The method of claim 15 , wherein the thermal process comprises an annealing process, and wherein a nitrogen gas is used in the annealing process.
17. The method of claim 14 , wherein:
a depth of the dipole layer penetrated into the first IL exceeds a depth of the dipole layer penetrated into the second IL; and
the depth of the dipole layer penetrated into the second IL exceeds a depth of the dipole layer penetrated into the third IL.
18. The method of claim 14 , wherein:
a concentration level of the dipole layer in the first IL exceeds a concentration level of the dipole layer in the second IL; and
the concentration level of the dipole layer in the second IL exceeds a concentration level of the dipole layer in the third IL.
19. The method of claim 14 , wherein the depositing comprises depositing lanthanum oxide, yttrium oxide, magnesium oxide, or strontium oxide as the dipole layer.
20. The method of claim 14 , further comprising:
before the forming the first gate dielectric, the forming the second gate dielectric, and the forming the third gate dielectric, removing the dipole layer and remaining portions of the first mask and the second mask.