Co-optimization of FinFET devices by source/drain modulation and structures thereof
Structures and methods for the co-optimization of various device types include performing a first photolithography and etch process to simultaneously form a first source/drain recess for a first device in a first substrate region and a third source/drain recess for a third device in a third substrate region different than the first substrate region. In some embodiments, the method further includes performing a second photolithography and etch process to form a second source/drain recess for a second device in a second substrate region different than the first and third substrate regions. The method further includes forming a first source/drain feature within the first source/drain recess, a second source/drain feature within the second source/drain recess, and a third source/drain feature within the third source/drain recess.
1 . A method of fabricating a semiconductor device, comprising:
performing a first photolithography and etch process to simultaneously form a first source/drain recess for a first device of a first doping type in a first substrate region and a third source/drain recess for a third device of the first doping type in a third substrate region different than the first substrate region;
performing a second photolithography and etch process to form a second source/drain recess for a second device of the first doping type in a second substrate region different than the first substrate region and the third substrate region, wherein:
the second source/drain recess extends into a first fin along a third direction,
the second source/drain recess is positioned between a first gate stack and a second gate stack arranged on the first fin along a first direction different than the third direction,
the first gate stack and the second gate stack extend lengthwise along a second direction different than the first direction and the third direction, and
a first gate spacer is adjacent the first gate stack along the first direction; and
forming a first source/drain feature of the first doping type within the first source/drain recess, a second source/drain feature of the first doping type within the second source/drain recess, and a third source/drain feature of the first doping type within the third source/drain recess, the second source/drain feature having a protrusion underlying the first gate spacer such that a line extending in the third direction passing through the first gate spacer passes through the protrusion.
2 . The method of claim 1 , wherein:
the first photolithography and etch process defines the first source/drain recess for a first N-type source/drain region of the first device,
the first photolithography and etch process defines the third source/drain recess for a third N-type source/drain region of the third device, and
the second photolithography and etch process defines the second source/drain recess for a second N-type source/drain region of the second device.
3 . The method of claim 1 , wherein:
the first photolithography and etch process defines the first source/drain recess for a first P-type source/drain region of the first device,
the first photolithography and etch process defines the third source/drain recess for a third P-type source/drain region of the third device, and
the second photolithography and etch process defines the second source/drain recess for a second P-type source/drain region of the second device.
4 . The method of claim 1 , wherein:
the first device comprises a system-on-a-chip (SOC) device,
the second device comprises a high-performance computing (HPC) device, and
the third device comprises an input/output (IO) device.
5 . The method of claim 1 , wherein:
the first device has a first contacted poly pitch (CPP),
the second device has a second CPP greater than the first CPP, and
the third device has a third CPP greater than the second CPP.
6 . The method of claim 1 , wherein:
the first device has a first source/drain proximity,
the second device has a second source/drain proximity less than the first source/drain proximity, and
the third device has a third source/drain proximity greater than the first source/drain proximity and the second source/drain proximity.
7 . The method of claim 1 , wherein the second photolithography and etch process further comprises a multi-step etch process.
8 . The method of claim 7 , wherein the multi-step etch process comprises a first etch step that forms a U-shaped source/drain recess and a second etch step that comprises an isotropic or wet etch that extends lateral boundaries of the U-shaped source/drain recess to form protrusions along sides of the second source/drain recess.
9 . The method of claim 1 , wherein the second photolithography and etch process comprises an isotropic or wet etch to form the second source/drain recess and to extend lateral boundaries of the second source/drain recess to form protrusions along sides of the second source/drain recess.
10 . The method of claim 1 , wherein:
the first source/drain recess has a first depth,
the second source/drain recess has a second depth,
the third source/drain recess has a third depth, and
the first depth is substantially equal to the second depth.
11 . A method, comprising:
providing a substrate comprising a plurality of regions, wherein each region of the plurality of regions comprises a different device type of the same doping type;
forming source/drain recesses within source/drain regions of each of the different device types in each region of the plurality of regions, wherein:
a first source/drain recess of the source/drain recesses for at least one device type in a first region of the plurality of regions is formed in a separate process from the source/drain recess for other device types in other regions of the plurality of regions different than the first region,
the first source/drain recess is formed in a first fin in the first region,
the first source/drain recess is between a first gate stack and a second gate stack arranged adjacent each other along a first direction, extending lengthwise along a second direction different than the first direction, and having height along a third direction different than the first direction and the second direction, and
the first source/drain recess underlies the first gate stack and the second gate stack such that a line extending in the third direction passes through the first source/drain recess and the first gate stack; and
epitaxially growing a source/drain feature in the source/drain recesses formed within the source/drain regions of each of the different device types in each region of the plurality of regions.
12 . The method of claim 11 , wherein the forming source/drain recesses comprises:
performing a first photolithography and etch process to form the source/drain recess for the at least one device type in the first region of the plurality of regions; and
performing a second photolithography and etch process to simultaneously form the source/drain recess for the other device types in the other regions of the plurality of regions different than the first region.
13 . The method of claim 11 , wherein the source/drain regions of each of the different device types in each region of the plurality of regions comprise N-type source/drain regions or P-type source/drain regions.
14 . The method of claim 11 , wherein the different device types in each region of the plurality of regions comprise a system-on-a-chip (SOC) device, a high-performance computing (HPC) device, and an input/output (IO) device.
15 . The method of claim 11 , wherein the at least one device type in the first region has a smaller source/drain proximity than the other device types in the other regions.
16 . The method of claim 11 , wherein formation of the source/drain recess for the at least one device type comprises an isotropic or wet etch that forms protrusions along sides of the source/drain recess for the at least one device type.
17 . The method of claim 11 , wherein:
the source/drain recess for the at least one device type in the first region has a first depth,
the source/drain recess for another device type in another region of the plurality of regions has a second depth, and
the first depth is substantially equal to the second depth.
18 . A method of fabricating a semiconductor device, comprising:
providing a semiconductor device comprising a first gate stack and a second gate stack arranged on a first fin and adjacent each other along a first direction in a second substrate region, at least one of the first gate stack or the second gate stack having length extending in a second direction different than the first direction and height extending in a third direction different than the first direction and the second direction;
performing a first photolithography and etch process to form a first source/drain recess for a first device of a first dopant type in a first substrate region and a third source/drain recess for a third device of the first dopant type in a third substrate region different than the first substrate region;
while the first source/drain recess and the second source/drain recess are protected by a mask, performing a second photolithography and etch process to form a second source/drain recess for a second device of the first dopant type between the first gate stack and the second gate stack in the second substrate region different than the first substrate region and the third substrate region and exposed through the mask, wherein the second photolithography and etch process removes material of the first fin along the third direction and the first direction such that a protrusion is defined along a side of the second source/drain recess, the protrusion underlying a gate spacer adjacent the first gate stack along the first direction; and
forming a first source/drain feature within the first source/drain recess, a second source/drain feature within the second source/drain recess, and a third source/drain feature within the third source/drain recess.
19 . The method of claim 18 , wherein the performing a second photolithography and etch process comprises performing the second photolithography and etch process such that the second source/drain recess underlies the first gate stack and a line extending in the third direction passes through the first gate stack and the second source/drain recess.
20 . The method of claim 18 , wherein:
the performing a first photolithography and etch process comprises performing a first dry etch, and
the performing a second photolithography and etch process comprises performing a second dry etch and performing a wet etch after the second dry etch.