IP Library Granted Patent US 12,648,191
Granted Patent B2
US 12,648,191 · App. 17/818,057 · Granted Jun 2, 2026

Transistor gate isolation structures and methods of forming the same

Inventors: Li-Fong Lin (Hsinchu, TW); Wen-Kai Lin (Yilan County, TW); Zhen-Cheng Wu (Hsinchu, TW); Chi On Chui (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H10D62/116H10D30/6211H10D30/6219H10D64/017H10D84/0151H10D84/038
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Quick Facts
Patent No.
US 12,648,191
App. No.
17/818,057
Granted
Jun 2, 2026
Kind
B2
Abstract

Transistor gate isolation structures and methods of forming the same are provided. In an embodiment, a device includes: an isolation region; a first gate structure on the isolation region; a second gate structure on the isolation region; and a gate isolation structure between the first gate structure and the second gate structure in a first cross-section, an upper portion of the gate isolation structure having a first concentration of an element, a lower portion of the gate isolation structure having a second concentration of the element, the first concentration different from the second concentration, the lower portion extending continuously along a sidewall of the first gate structure, beneath the upper portion, and along a sidewall of the second gate structure.

Claims (44)

1 . A method comprising:

dividing a first gate structure into a plurality of second gate structures by etching an opening through the first gate structure, the opening physically separating the first gate structure into the second gate structures;

depositing an isolation layer in the opening, the isolation layer comprising an expandable dielectric material;

expanding the isolation layer in the opening by treating the expandable dielectric material; and

removing portions of the isolation layer over the second gate structures, a remaining portion of the isolation layer in the opening forming a gate isolation structure between the second gate structures.

2 . The method of claim 1 , wherein treating the expandable dielectric material comprises annealing the isolation layer in an oxygen-containing environment.

3 . The method of claim 1 , wherein treating the expandable dielectric material comprises bombarding the isolation layer with ions of an element that induces cross-linking of the expandable dielectric material.

4 . The method of claim 3 , wherein bombarding the isolation layer comprises generating a plasma from oxygen gas or ammonia.

5 . The method of claim 3 , further comprising:

performing a first pre-treatment process to shrink the isolation layer.

6 . The method of claim 5 , further comprising:

performing a second pre-treatment process to clean surface impurities from the isolation layer.

7 . The method of claim 1 , wherein the expandable dielectric material is a nitrogen-rich dielectric material.

8 . A method comprising:

etching an opening between a first gate structure and a second gate structure;

forming a gate isolation structure between the first gate structure and the second gate structure by:

depositing an isolation layer in the opening between the first gate structure and the second gate structure, wherein depositing the isolation layer forms a seam in the gate isolation structure, the seam comprising a portion of the opening unfilled by the isolation layer; and

shrinking the seam in the isolation layer by expanding the isolation layer, wherein expanding the isolation layer comprises increasing a concentration of an element in a material of the isolation layer;

forming an inter-layer dielectric over the gate isolation structure, the first gate structure, and the second gate structure; and

forming a first contact and a second contact through the inter-layer dielectric, the gate isolation structure disposed between the first contact and the second contact.

9 . The method of claim 8 , further comprising:

forming a first source/drain region and a second source/drain region, the first source/drain region disposed adjacent the first gate structure, the second source/drain region disposed adjacent the second gate structure, the first contact connected to the first source/drain region, the second contact connected to the second source/drain region.

10 . The method of claim 9 , further comprising:

etching the opening between a first gate spacer and a second gate spacer, the gate isolation structure formed between the first gate spacer and the second gate spacer, the first gate spacer disposed between the first source/drain region and the first gate structure, the second gate spacer disposed between the second source/drain region and the second gate structure.

11 . The method of claim 8 , wherein increasing the concentration of the element comprises:

bombarding the isolation layer with ions in a plasma treatment process to induce cross-linking of the material of the isolation layer at sidewalls of the seam, wherein the cross-linking chemically bonds opposing portions of the isolation layer to one another at an interface.

12 . The method of claim 11 , wherein the element is oxygen, and wherein bombarding the isolation layer comprises generating a plasma from an oxygen source precursor to form Si—O—Si bonds across the interface.

13 . The method of claim 11 , wherein the element is nitrogen, and wherein bombarding the isolation layer comprises generating a plasma from a nitrogen source precursor to form Si—N—Si bonds across the interface.

14 . The method of claim 11 , further comprising:

performing a first pre-treatment process before bombarding the isolation layer with ions, wherein the first pre-treatment process comprises shrinking the material of the isolation layer; and

performing a second pre-treatment process after the first pre-treatment process and before bombarding the isolation layer with ions, wherein the second pre-treatment process comprises cleaning surface impurities from the isolation layer.

15 . A method comprising:

dividing a first gate structure into a plurality of second gate structures by etching an opening through the first gate structure, the opening physically separating the first gate structure into the second gate structures;

forming a gate isolation structure between the second gate structures by:

depositing an isolation layer in the opening, the isolation layer comprising an expandable dielectric material; and

expanding the isolation layer in the opening by bombarding the isolation layer with ions of an element that induces cross-linking of the expandable dielectric material; and

forming an inter-layer dielectric over the gate isolation structure and the second gate structures.

16 . The method of claim 15 , wherein an upper portion of the isolation layer has a first concentration of the element, a lower portion of the isolation layer has a second concentration of the element, and the second concentration is less than the first concentration.

17 . The method of claim 15 , wherein the element is oxygen.

18 . The method of claim 15 , wherein the element is nitrogen.

19 . The method of claim 15 , wherein depositing the isolation layer forms a seam in the gate isolation structure, and cross-linking of the expandable dielectric material chemically bonds portions of the isolation layer at sidewalls of the seam to one another.

20 . The method of claim 15 , further comprising, before expanding the isolation layer:

shrinking the isolation layer by performing a first pre-treatment process; and

cleaning the isolation layer by performing a second pre-treatment process after the first pre-treatment process.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 31, 2022
From: LIN, LI-FONG; LIN, WEN-KAI; WU, ZHEN-CHENG; CHUI, CHI ON
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 060950/0795 →
Continuity (2)
Provisional Application 63364822 · May 17, 2022
Related Publication 20230378256A1 · Nov 23, 2023
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