Metallic sealants in transistor arrangements
Disclosed herein are transistor electrode-channel arrangements, and related methods and devices. For example, in some embodiments, a transistor electrode-channel arrangement may include a channel material, source/drain electrodes provided over the channel material, and a sealant at least partially enclosing one or more of the source/drain electrodes, wherein the sealant includes one or more metallic conductive materials.
1 . An integrated circuit (IC) device, comprising:
a semiconductor material;
a transistor comprising an electrode and a gate stack, wherein the electrode is a source electrode or a drain electrode of the transistor, and wherein the gate stack includes a gate dielectric and a gate electrode material; and
a sealant, wherein at least 80% of the sealant is amorphous, and wherein the electrode is between the semiconductor material and at least a portion of the sealant.
2 . The IC device according to claim 1 , wherein a hydrogen permeability coefficient of the sealant is above 10 −4 mole per millisecond Pascal.
3 . The IC device according to claim 1 , wherein the sealant includes one or more metallic conductive materials.
4 . The IC device according to claim 1 , wherein the sealant is over at least one sidewall of the electrode.
5 . The IC device according to claim 1 , wherein the sealant wraps around at least a portion of the electrode.
6 . The IC device according to claim 1 , wherein the sealant has a thickness between 0.5 and 100 nanometers.
7 . The IC device according to claim 1 , wherein the semiconductor material is a thin-film semiconductor material.
8 . The IC device according to claim 1 , wherein:
the IC device is a computing device that includes an IC die, and
the IC die includes the semiconductor material, the electrode, and the sealant.
9 . The IC device according to claim 8 , wherein the computing device is a wearable or handheld computing device.
10 . The IC device according to claim 8 , wherein the computing device further includes one or more communication chips and an antenna.
11 . An integrated circuit (IC) device, comprising:
a transistor comprising a region, wherein the region is either a source region or a drain region of the transistor;
an electrode coupled to the region;
a layer comprising two or more layers of different metallic conductive materials, wherein at least a portion of the layer is in physical contact with at least a portion of the electrode, and the layer includes an amorphous material; and
a semiconductor material, wherein the electrode is between the semiconductor material and at least a portion of the layer.
12 . The IC device according to claim 11 , wherein the layer has a thickness between 0.5 and 100 nanometers.
13 . The IC device according to claim 11 , wherein:
the IC device is an IC package that includes an IC die and a further component coupled to the IC die, and
the IC die includes the transistor, the electrode, and the layer.
14 . The IC device according to claim 13 , wherein the further component includes one of an interposer, a package substrate, a carrier substrate, a motherboard, or a further IC die.
15 . The IC device according to claim 13 , wherein the further component is coupled to the IC die by first-level interconnects.
16 . The IC device according to claim 11 , wherein the layer is over at least one sidewall of the electrode.
17 . The IC device according to claim 11 , wherein the transistor is a thin-film transistor.
18 . An integrated circuit (IC) device, comprising:
a transistor comprising an electrode and a gate stack, wherein the electrode is a source electrode or a drain electrode of the transistor, and wherein the gate stack includes a gate dielectric and a gate electrode material; and
a layer adjacent to the electrode, wherein at least 80 % of the layer is amorphous, at least a portion of the layer is in physical contact with at least a portion of the electrode, and the layer wraps around at least a portion of the electrode.
19 . The IC device according to claim 18 , wherein a hydrogen permeability coefficient of the layer is above 10 −4 mole per millisecond Pascal.
20 . The IC device according to claim 18 , wherein the layer includes one or more metallic conductive materials.
21 . The IC device according to claim 18 , further comprising:
a semiconductor material,
wherein the electrode is between the semiconductor material and at least a portion of the layer.
22 . The IC device according to claim 18 , wherein:
the IC device is an IC package that includes an IC die and a further component coupled to the IC die, and
the IC die includes the transistor and the layer.
23 . The IC device according to claim 22 , wherein the further component includes one of an interposer, a package substrate, a carrier substrate, a motherboard, or a further IC die.