Device and method for measuring a duty cycle of a clock signal
View Patent ↗A duty cycle measurement (DCM) device includes a charge pump circuit and a clocked comparator circuit. The charge pump circuit is configured to receive a clock signal that has an unknown duty cycle and to generate a capacitor voltage based on the duty cycle of the clock signal. The clocked comparator circuit is configured to receive the capacitor voltage and a reference voltage and to generate a digital output code based on the capacitor voltage and the reference voltage. The digital output code is indicative of the duty cycle of the clock signal. The charge pump circuit is further configured to receive the digital output code. A method of determining a duty cycle of a clock signal is also disclosed.
1. A duty cycle measurement (DCM) device comprising:
a charge pump circuit configured to receive a clock signal that has an unknown duty cycle and to generate a capacitor voltage based on the duty cycle of the clock signal, wherein the charge pump circuit comprises at least one current source having a first current source terminal connected to a capacitor voltage node, a second current source terminal connected to an electrical ground, and a third current source terminal configured to receive the clock signal; and
a clocked comparator circuit configured to receive the capacitor voltage and a reference voltage and to generate a digital output code based on the capacitor voltage and the reference voltage, wherein the digital output code is indicative that the duty cycle of the clock signal is about 50%, wherein the charge pump circuit is further configured to receive the digital output code.
2. The DCM device of claim 1 , wherein the charge pump circuit includes:
a first current source having a first current source terminal configured to receive a supply voltage, a second current source terminal connected to the capacitor voltage node, and a third current source terminal configured to receive the digital output code;
a second current source having a first current source terminal connected to the capacitor voltage node, a second current source terminal connected to the electrical ground, and a third current source terminal configured to receive the clock signal; and
a capacitor connected between the capacitor voltage node and the electrical ground.
3. The DCM device of claim 2 , wherein the clocked comparator circuit includes a comparator having an inverting terminal connected to the capacitor voltage node and a non-inverting terminal configured to receive the reference voltage.
4. The DCM device of claim 3 , wherein the clocked comparator circuit further includes a latch having a first latch terminal connected to the comparator and a second latch terminal connected to the third current source terminal of the first current source.
5. The DCM device of claim 4 , wherein the latch further includes a third latch terminal configured to receive the clock signal.
6. A duty cycle measurement (DCM) device comprising:
a clock select circuit configured to provide a first clock signal that has predetermined duty cycle;
a charge pump circuit configured to receive the first clock signal and to generate a capacitor voltage based on a duty cycle of the first clock signal, wherein the charge pump circuit comprises at least one current source having a first current source terminal connected to a capacitor voltage node, a second current source terminal connected to an electrical ground, and a third current source terminal configured to receive the first clock signal; and
a clocked comparator circuit configured to receive the capacitor voltage and a reference voltage and to generate a digital output code based on the capacitor voltage and the reference voltage, wherein the digital output code is indicative that the duty cycle of the first clock signal is about 50%, wherein the charge pump circuit is further configured to receive the digital output code.
7. The DCM device of claim 6 , wherein the charge pump circuit includes:
a first current source having a first current source terminal configured to receive a supply voltage, a second current source terminal connected to the capacitor voltage node, and a third current source terminal configured to receive the digital output code;
a second current source having a first current source terminal connected to the capacitor voltage node, a second current source terminal connected to the electrical ground, and a third current source terminal configured to receive the first clock signal; and
a capacitor connected between the capacitor voltage node and the electrical ground.
8. The DCM device of claim 7 , wherein the clocked comparator circuit includes a comparator having an inverting terminal connected to the capacitor voltage node and a non-inverting terminal configured to receive the reference voltage.
9. The DCM device of claim 8 , wherein the clocked comparator circuit further includes a latch having a first latch terminal connected to an output of the comparator and a second latch terminal connected to the third current source terminal of the first current source.
10. The DCM device of claim 9 , wherein the latch further includes a third latch terminal configured to receive the first clock signal.
11. The DCM device of claim 6 , wherein the clock select circuit is further configured to receive a second clock signal that has an unknown duty cycle and a clock select signal and to provide at the output thereof one of the first and second clock signals based on the clock select signal.
12. The DCM device of claim 6 , wherein the clock select circuit includes a frequency divider configured to receive a second clock signal and to divide a frequency of the second clock signal to obtain the first clock signal.
13. The DCM device of claim 12 , wherein the clock select circuit further includes a multiplexer configured to receive the first and second clock signals.
14. A method of determining a duty cycle of a clock signal, the method comprising:
operating in a calibration mode;
receiving, by a source current, a first clock signal that has a predetermined duty cycle, wherein the current source has a first current source terminal connected to a capacitor voltage node, a second current source terminal connected to an electrical ground, and a third current source terminal configured to receive the first clock signal;
generating a first capacitor voltage based on the duty cycle of the first clock signal;
comparing the first capacitor voltage with a reference voltage;
generating a first digital output code based on the result of the comparison and indicative that the duty cycle of the first clock signal is about 50%; and
receiving the first digital output code.
15. The method of claim 14 , wherein operating in the calibration mode includes:
receiving a second clock signal;
dividing a frequency of the second clock signal to obtain the first clock signal;
receiving a clock select signal; and
providing the first clock signal as an output based on the clock select signal.
16. The method of claim 14 , wherein generating the first capacitor voltage includes charging and discharging a capacitor based on the duty cycle of the first clock signal.
17. The method of claim 14 , further comprising:
operating in a measurement mode;
receiving a second clock signal that has an unknown duty cycle;
generating a second capacitor voltage based on the duty cycle of the second clock signal;
comparing the second capacitor voltage with the reference voltage;
generating the second digital output code based on the result of the comparison; and
receiving the second digital output code.
18. The method of claim 17 , wherein operating in the measurement mode includes:
receiving a second clock signal;
dividing a frequency of the second clock signal to obtain the first clock signal;
receiving a clock select signal; and
providing the second clock signal as an output based on the clock select signal.
19. The method of claim 17 , wherein generating the second capacitor voltage includes charging and discharging a capacitor based on the duty cycle of the second clock signal.
20. The method of claim 17 , further comprising:
providing the first digital output code as an output; and
providing the second digital output code as an output.