Dielectric engineered tunnel region in memory cells
A variety of applications can include memory devices having memory cells, where each memory cell can have an engineered tunnel region between a channel structure of the memory cell and a charge storage region of the memory cell. The engineered tunnel region can be directed to improved read, program, and retention operations of the memory region. In various embodiments, the engineered tunnel region can have multiple dielectric regions with a dielectric constant modulation by inserting material having a dielectric constant that is low relative to silicon nitride and material having a dielectric constant that is high relative to silicon nitride. In various embodiments, the engineered tunnel region of a memory cell can have multiple dielectric regions with material having deep traps near the charge storage region of the memory cell. Other engineered tunnel regions are disclosed.
1 . A memory device comprising:
an array of memory cells, each memory cell having a charge storage region separated from a channel structure by a tunnel region, the tunnel region having multiple regions including:
a first dielectric region adjacent to and contacting the channel structure, material of the first dielectric region being different from silicon oxide and having a dielectric constant less than that of silicon nitride, the first dielectric region being silicon oxynitride doped with carbon and boron;
one or more additional dielectric regions between the first dielectric region and the charge storage region, the one or more additional dielectric regions including a second dielectric region having a dielectric constant greater than that of silicon nitride.
2 . The memory device of claim 1 , wherein the first dielectric region has a lowest dielectric constant of the multiple regions of the tunnel region.
3 . The memory device of claim 1 , wherein the one or more additional dielectric regions include a third dielectric region between the first dielectric region and the second dielectric region, material of the third dielectric region being a doped silicon oxynitride having a different compositional content from the material of the first dielectric region.
4 . The memory device of claim 3 , wherein the doped silicon oxynitride of the third dielectric region is doped with carbon or boron, the third dielectric region having a different nitrogen content than the first dielectric region.
5 . The memory device of claim 1 , wherein the second dielectric region is adjacent to and contacts the first dielectric region and the one or more additional dielectric regions includes a third dielectric region and a fourth dielectric region between the second dielectric region and the charge storage region, dielectric constants of the third dielectric region and the fourth dielectric region being different from each other and less than that of silicon nitride.
6 . A memory device comprising:
an array of memory cells, each memory cell having a charge storage region separated from a channel structure by a tunnel region, the tunnel region having multiple regions including:
a first dielectric region adjacent to and contacting the channel structure, material of the first dielectric region being different from silicon oxide and having a dielectric constant less than that of silicon nitride;
one or more additional dielectric regions between the first dielectric region and the charge storage region, the one or more additional dielectric regions including a second dielectric region having a dielectric greater than that of silicon nitride, wherein:
the second dielectric region is adjacent to and contacts the first dielectric region; and
the one or more additional dielectric regions include:
a third dielectric region having a dielectric constant greater than that of silicon nitride, the third dielectric region being adjacent to and contacting the second dielectric region, dielectric constants of the second dielectric region and the third dielectric region being different from each other; and
a fourth dielectric region between the third dielectric region and the charge storage region, the fourth dielectric region having a dielectric constant less than that of silicon nitride.
7 . The memory device of claim 1 , wherein the one or more additional dielectric regions include dielectric non-metal oxide regions with material of each dielectric non-metal oxide region including silicon oxynitride doped with carbon or boron, with silicon oxynitride in different dielectric non-metal oxide regions having a different nitrogen profile or a different doping profile.
8 . The memory device of claim 1 , wherein the second dielectric region includes a metal oxide.
9 . The memory device of claim 8 , wherein material of the second dielectric region includes a dielectric single metal oxide or a dielectric double metal oxide.
10 . The memory device of claim 9 , wherein metal in the single metal oxide or double metal oxide includes one or more of hafnium, zirconium, or aluminum.
11 . A memory device comprising;
an array of memory cells, each memory cell having a charge storage region separated from a channel structure by a tunnel region, the tunnel region having multiple regions including:
a silicon oxynitride region adjacent to and contacting the charge storage region, the silicon oxynitride having varying content of nitrogen as a function of distance across the silicon oxynitride; and
a silicon oxide region adjacent to and contacting the channel structure, the silicon oxide region being undoped silicon dioxide.
12 . The memory device of claim 11 , wherein the silicon oxide region has a thickness equal to or less than one-half of a thickness of the silicon oxynitride region.
13 . The memory device of claim 11 , wherein the silicon oxide region has a thickness equal to or less than one-third of a thickness of the silicon oxynitride region.
14 . The memory device of claim 11 , wherein the silicon oxynitride region includes multiple sub-regions of silicon oxynitride having different nitrogen concentrations as a function of distance across the respective sub-regions.
15 . The memory device of claim 11 , wherein the charge storage region includes silicon nitride and the channel structure includes polysilicon.