Method of forming FinFET with low-dielectric-constant gate electrode spacers

1. A method, comprising:

forming a gate stack over a fin of a substrate;

sequentially depositing a first dielectric layer, a second dielectric layer, a third dielectric layer, and a filling dielectric over the gate stack, wherein the second dielectric layer has a lower dielectric constant than dielectric constants of the first and third dielectric layers;

forming a dielectric cap over the first, second, third dielectric layers and the filling dielectric;

etching the dielectric cap, the first, second, third dielectric layers, and the filling dielectric simultaneously, to form gate spacers on opposite sidewalls of the gate stack and expose a top surface of the fin, wherein each of the gate spacers comprises remaining portions of the dielectric cap and the first, second, and third dielectric layers; and

after the gate spacers are formed, forming an epitaxy source/drain structure in contact with one of the gate spacers and the top surface of the fin.

2. The method of claim 1 , further comprising prior to forming the dielectric cap, performing a chemical mechanical polishing process on the filling dielectric until a top surface of the gate stack is exposed.

3. The method of claim 2 , further comprising prior to forming the dielectric cap, etching back the first, second, third dielectric layers and the filling dielectric to expose the opposite sidewalls of the gate stack.

4. The method of claim 1 , further comprising performing a chemical mechanical polishing process on the dielectric cap until a top surface of the gate stack is exposed.

5. The method of claim 1 , wherein etching the dielectric cap, the first, second, third dielectric layers, and the filling dielectric further comprises removing a portion of the fin.

6. The method of claim 1 , wherein etching the dielectric cap, the first, second, third dielectric layers, and the filling dielectric is performed such that an entirety of the filling dielectric is removed.

7. The method of claim 1 , wherein the first and third dielectric layers and the dielectric cap are made of SiOC.

8. A method, comprising:

forming first and second gate stacks over a fin of a substrate;

sequentially depositing a first dielectric layer, a second dielectric layer, and a third dielectric layer lining sidewalls of the first and second gate stacks and a top surface of the fin, wherein the second dielectric layer has a lower dielectric constant than dielectric constants of the first and third dielectric layers;

depositing a filling dielectric over the gate stack, wherein the filling dielectric overfills a space between the first and second gate stacks;

etching back the first, second, third dielectric layers and the filling dielectric;

forming a dielectric cap over the first, second, third dielectric layers and the filling dielectric, wherein a portion of the filling dielectric between the first and second gate stacks is sealed by the third dielectric layer and the dielectric cap;

etching the dielectric cap, the first, second, third dielectric layers, and the filling dielectric simultaneously, to form first gate spacers on the sidewalls of the first gate stack and second gate spacers on the sidewalls of the second gate stack; and

forming an epitaxy source/drain structure over the fin.

9. The method of claim 8 , wherein the first gate stack comprises a gate electrode and a gate mask over the gate electrode, and wherein etching back the first, second, third dielectric layers and the filling dielectric is performed such that topmost ends of the first, second, third dielectric layers and the filling dielectric are lower than an interface between the gate electrode and the gate mask.

10. The method of claim 8 , further comprising, prior to etching back the first, second, third dielectric layers and the filling dielectric, performing a chemical mechanical polishing process on the first, second, third dielectric layers and the filling dielectric to expose top surfaces of the first and second gate stacks.

11. The method of claim 8 , wherein the dielectric cap is in contact with a top surface of the portion of the filing dielectric, and the third dielectric layer is in contact with a bottom surface and opposite sidewalls of the portion of the filing dielectric.

12. The method of claim 8 , wherein prior to etching the dielectric cap, the first, second, third dielectric layers, and the filling dielectric, portions of the first, second, third dielectric layers between the first and second gate stacks have U-shape cross-section, while the dielectric cap has a bar-shape cross-section.

13. The method of claim 8 , further comprising replacing the first and second gate stacks with first and second metal gate stacks.

14. The method of claim 8 , wherein etching the dielectric cap, the first, second, third dielectric layers, and the filling dielectric is performed such that an entirety of the portion of the filling dielectric is removed.

15. The method of claim 8 , wherein the first and third dielectric layers and the dielectric cap are made of SiOC.

16. A method, comprising:

forming a gate stack over a fin of a substrate, wherein the gate stack comprises a gate dielectric, a gate electrode, and a gate mask over the gate electrode;

sequentially depositing a first dielectric layer, a second dielectric layer, a third dielectric layer, and a filling dielectric over the gate stack, wherein the second dielectric layer has a lower dielectric constant than dielectric constants of the first and third dielectric layers;

etching back the first, second, third dielectric layers and the filling dielectric, such that top surfaces of the first, second, third dielectric layers and the filling dielectric are lower than an interface between the gate electrode and the gate mask;

forming a dielectric cap over the top surfaces of the first, second, third dielectric layers and the filling dielectric;

etching the dielectric cap, the first, second, third dielectric layers, and the filling dielectric simultaneously, to form gate spacers on opposite sidewalls of the gate stack and expose a top surface of the fin; and

after etching the dielectric cap, the first, second, third dielectric layers, and the filling dielectric, forming an epitaxy source/drain structure over the fin.

17. The method of claim 16 , further comprising:

forming an interlayer dielectric (ILD) layer over the epitaxy source/drain structure, wherein a top surface of the ILD layer is level with a top surface of the dielectric cap; and

forming a contact plug in the ILD layer and in contact with the epitaxy source/drain structure, wherein the top surface of the ILD layer is level with a top surface of the contact plug.

18. The method of claim 16 , wherein etching the dielectric cap, the first, second, third dielectric layers, and the filling dielectric comprises lowering a top surface of the fin.

19. The method of claim 16 , wherein the third dielectric layer extends along a sidewall and a bottom surface of the filling dielectric.

20. The method of claim 16 , wherein a bottom surface of the filling dielectric is higher than a bottom surface of the gate stack.