Semiconductor structure with modified spacer and method for forming the same
Semiconductor structures and methods for manufacturing the same are provided. The method for manufacturing the semiconductor structure includes forming a fin structure protruding from a substrate, and the fin structure includes first semiconductor material layers and second semiconductor material layers alternately stacked. The method also includes forming a dummy gate structure across the fin structure and forming a gate spacer on a sidewall of the dummy gate structure. The method also includes partially oxidizing the gate spacer to form an oxide layer and removing the oxide layer to form a modified gate spacer. The method also includes removing the first semiconductor material layers to form gaps and forming a gate structure in the gaps to wrap around the second semiconductor material layers and over the second semiconductor material layers to cover the modified gate spacer.
1 . A method for manufacturing a semiconductor structure, comprising:
forming a fin structure protruding from a substrate, wherein the fin structure comprises first semiconductor material layers and second semiconductor material layers alternately stacked;
forming a dummy gate structure across a channel region of the fin structure;
forming a gate spacer on a sidewall of the dummy gate structure;
recessing a source/drain region of the fin structure to form a source/drain recess;
forming a source/drain feature over the source/drain recess;
depositing a contact etch stop layer (CESL) over the source/drain recess;
depositing an interlayer dielectric (ILD) layer over the CESL;
replacing a top portion of the ILD layer with a mask feature;
recessing the dummy gate structure until a top surface of the dummy gate structure is lower than a bottom surface of the mask feature;
after the recessing the dummy gate structure, etching the gate spacer above the recessed dummy gate structure to form shortened gate spacer;
after the etching of the gate spacer, removing the recessed dummy gate structure;
after the removing of the recessed dummy gate structure, partially oxidizing the gate spacer to form an oxide layer;
removing the oxide layer to form a modified gate spacer;
removing the first semiconductor material layers over the channel region to form gaps; and
forming a gate structure in the gaps to wrap around the second semiconductor material layers and over the second semiconductor material layers to cover the modified gate spacer.
2 . The method for manufacturing the semiconductor structure as claimed in claim 1 , wherein the modified gate spacer has a sloped sidewall in direct contact with the gate structure.
3 . The method for manufacturing the semiconductor structure as claimed in claim 2 , wherein a bottom portion of the modified gate spacer is wider than a top portion of the modified gate spacer.
4 . The method for manufacturing the semiconductor structure as claimed in claim 3 , further comprising:
removing an upper portion of the gate structure to form a recess; and
forming a mask structure in the recess, wherein a top surface of the mask structure is wider than a bottom surface of the mask structure.
5 . The method for manufacturing the semiconductor structure as claimed in claim 4 , wherein the mask structure is in contact with the modified gate spacer.
6 . The method for manufacturing the semiconductor structure as claimed in claim 1 , further comprising:
recessing the dummy gate structure to form a trench exposing a first sidewall of the gate spacer before partially oxidizing the gate spacer to form the oxide layer; and
partially removing the gate spacer from the trench.
7 . The method for manufacturing the semiconductor structure as claimed in claim 6 , further comprising:
forming a source/drain structure attached to the second semiconductor material layers;
forming a contact etch stop layer over the source/drain structure and covering a second sidewall of the gate spacer; and
forming an interlayer dielectric layer over the contact etch stop layer,
wherein the contact etch stop layer is exposed by the trench after partially removing the gate spacer from the trench and is also partially oxidized to form the oxide layer.
8 . The method for manufacturing the semiconductor structure as claimed in claim 7 , wherein a portion of the interlayer dielectric layer is exposed by the trench after removing the oxide layer to form the modified gate spacer.
9 . A method for manufacturing a semiconductor structure, comprising:
alternately stacking first semiconductor material layers and second semiconductor material layers to form a semiconductor stack over a substrate;
patterning the semiconductor stack to form a fin structure;
forming a dummy gate structure across a channel region of the fin structure, wherein the dummy gate structure comprises a dummy oxide layer and a dummy gate electrode layer;
forming gate spacers on sidewalls of the dummy gate structure;
recessing a source/drain region of the fin structure to form a source/drain recess;
forming a source/drain feature over the source/drain recess;
depositing a contact etch stop layer (CESL) over the source/drain recess;
depositing an interlayer dielectric (ILD) layer over the CESL;
replacing a top portion of the ILD layer with a mask feature;
removing an upper portion of dummy gate electrode layer to form a trench over a lower portion of the dummy gate electrode layer, a top surface of the lower portion being lower than a bottom surface of the mask feature;
after the removing of the upper portion of the dummy gate electrode layer, etching the gate spacers from the trench to form shortened gate spacers;
oxidizing the shortened gate spacers to form an oxide layer;
removing the oxide layer;
removing the first semiconductor material layers over the channel region of the fin structure; and
forming a gate structure wrapping around the second semiconductor material layers.
10 . The method for manufacturing the semiconductor structure as claimed in claim 9 , further comprising:
removing a bottom portion of the dummy gate electrode layer to expose the dummy oxide layer before oxidizing the gate spacers to form the oxide layer.
11 . The method for manufacturing the semiconductor structure as claimed in claim 9 , further comprising:
oxidizing a topmost layer of the second semiconductor material layers to form a thickened dummy oxide layer; and
removing the thickened dummy oxide layer.
12 . The method for manufacturing the semiconductor structure as claimed in claim 11 , wherein the topmost layer of the second semiconductor material layers is thicker than a bottommost layer of the second semiconductor material layers before patterning the semiconductor stack to form the fin structure.
13 . The method for manufacturing the semiconductor structure as claimed in claim 11 , wherein a portion of the topmost layer of the second semiconductor material layers in contact with the gate structure is thinner than a bottommost layer of the second semiconductor material layers after removing the thickened dummy oxide layer.
14 . The method for manufacturing the semiconductor structure as claimed in claim 9 , further comprising:
forming source/drain structures attached to opposite sides of the second semiconductor material layers;
forming a contact etch stop layer over the source/drain structures and covering sidewalls of the gate spacers; and
partially oxidizing the contact etch stop layer to form the oxide layer.
15 . A method, comprising:
forming, over a substrate, a fin-shaped structure that includes first semiconductor layers interleaved by second semiconductor layers;
forming a dummy gate structure over a channel region of the fin-shaped structure;
depositing a spacer layer over the dummy gate structure and the fin-shaped structure;
anisotropically etching a source/drain region of the fin-shaped structure to form a source/drain recess and to pattern the spacer layer to form a gate spacer along a sidewall of the dummy gate structure;
forming a source/drain feature over the source/drain recess;
depositing a contact etch stop layer over the source/drain feature;
depositing an interlayer dielectric layer over the contact etch stop layer;
partially removing a top portion of the interlayer dielectric layer to form a top recess;
after the partially removing, depositing a mask layer over the top recess;
after the depositing of the mask layer, removing an upper portion of dummy gate electrode layer to form a trench over a lower portion of the dummy gate electrode layer;
after the removing of the upper portion of the dummy gate electrode, etching the gate spacer from the trench to form shortened gate spacer;
after the etching of the gate spacers, oxidizing the shortened gate spacers to form an oxide layer;
removing the oxide layer;
selectively removing the first semiconductor layers in the channel region of the fin-shaped structure to form a plurality of channel layers from the second semiconductor layers; and
forming a gate structure to wrap around each of the plurality of channel layers.
16 . The method of claim 15 , further comprising:
laterally recessing the first semiconductor layers to form notches; and
forming inner spacers in the notches.
17 . The method of claim 15 , wherein the forming of the source/drain feature comprises:
depositing a leakage blocking layer to interface the substrate; and
depositing first epitaxial layer to interface the leakage blocking layer and sidewalls of the second semiconductor layers exposed in the source/drain recess.
18 . The method of claim 15 , wherein the mask layer comprises SiN, SiCN, SiOC, SiOCN, HfO 2 , ZrO 2 , HfAlO, HfSiO, or Al 2 O 3 .
19 . The method of claim 15 , wherein the etching of the gate spacer comprises use of CF 4 or HF.
20 . The method of claim 15 , wherein the oxidizing comprises use of a decoupled plasma oxide (DPO) process.