Method for forming ohmic contacts on compound semiconductor devices
A method for forming ohmic contacts on a compound semiconductor device is disclosed. A channel layer is formed on a substrate. A barrier layer is formed on the channel layer. A passivation layer is formed on the barrier layer. A contact area is formed by etching through the passivation layer and the barrier layer. The channel layer is partially exposed at a bottom of the contact area. A sacrificial metallic layer is conformally deposited on the contact area. The sacrificial metallic layer is subjected to an annealing process, thereby forming a heavily doped region in the channel layer directly under the sacrificial metallic layer. The sacrificial metallic layer is removed to expose the heavily doped region. A metal silicide layer is formed on the heavily doped region.
1 . A method for forming an ohmic contact on a compound semiconductor device, comprising:
providing a substrate;
forming a channel layer on the substrate;
forming a barrier layer on the channel layer;
forming a passivation layer on the barrier layer;
forming a contact area by etching through the passivation layer and the barrier layer, wherein the channel layer is partially exposed at a bottom of the contact area, wherein a remainder of the barrier layer and the passivation layer constitutes an island area located next to the contact area;
conformally depositing a sacrificial metallic layer on the contact area and on a sidewall and a top surface of the remainder of the barrier layer and the passivation layer, wherein the sacrificial metallic layer comprises a Ti layer;
subjecting the sacrificial metallic layer to an annealing process, wherein the Ti layer reacts with the channel layer to form a TiN layer thereby forming a heavily doped region in the channel layer directly under the sacrificial metallic layer within the contact area;
removing the sacrificial metallic layer to expose the heavily doped region, wherein the sacrificial metallic layer is removed by performing a dry etching process, wherein the dry etching process comprises a step of increasing nitrogen vacancy in the contact area by over-etching the channel layer using BCl 3 ; and
forming a metal silicide layer on the heavily doped region.
2 . The method according to claim 1 , wherein the sacrificial metallic layer further comprises another TiN layer on the Ti layer.
3 . The method according to claim 2 , wherein the Ti layer has a thickness of 500-1000 angstroms and the another TiN layer has a thickness of less than or equal to 500 angstroms.
4 . The method according to claim 1 , wherein the heavily doped region is an N ++ region.
5 . The method according to claim 4 , wherein a spacer comprising remainder of the sacrificial metallic layer is left on a sidewall of the passivation layer and a sidewall of the barrier layer.
6 . The method according to claim 1 , wherein the heavily doped region is an N + region.
7 . The method according to claim 6 , wherein the sacrificial metallic layer is removed by performing a wet etching process.
8 . The method according to claim 7 , wherein the wet etching process comprises sulfuric acid peroxide mixture (SPM) cleaning.
9 . The method according to claim 1 , wherein the channel layer comprises GaN.
10 . The method according to claim 1 , wherein the channel layer is an un-doped GaN layer.
11 . The method according to claim 1 , wherein the barrier layer comprises AlGaN.
12 . The method according to claim 1 further comprising:
forming two-dimensional electron gas at an interface between the channel layer and the barrier layer.
13 . The method according to claim 1 further comprising:
forming a buffer layer on the substrate; and
forming the channel layer on the buffer layer, wherein the buffer layer has a band gap larger than that of the channel layer.
14 . The method according to claim 13 , wherein the buffer layer comprises AlN, AlGaN, or GaN.
15 . The method according to claim 1 , wherein the passivation layer comprises silicon nitride, silicon oxide, aluminum oxide, hafnium oxide, or aluminum nitride.
16 . The method according to claim 1 , wherein the substrate comprises SiC, Sapphire, Si, Al 2 O 3 , AlN, or GaN.
17 . The method according to claim 1 , wherein the channel layer and the barrier layer are epitaxially grown on the substrate.