Semiconductor memory device and method of manufacturing semiconductor memory device
A semiconductor memory device according to an embodiment includes: a stacked body in which a plurality of first conductive layers and a plurality of first insulating layers are stacked alternatively, the stacked body including a staircase portion obtained by processing the plurality of first conductive layers in a staircase pattern; a pillar extending in a stacking direction of the stacked body in the stacked body away from the staircase portion in a first direction intersecting the stacking direction; and a contact disposed in the staircase portion and connected to one first conductive layer out of the plurality of first conductive layers, in which the contact includes a second conductive layer extending from above the staircase portion to the one first conductive layer and integrated with the one first conductive layer.
1 . A semiconductor memory device comprising:
a stacked body in which a plurality of first conductive layers and a plurality of first insulating layers are stacked alternatively, the stacked body including a staircase portion obtained by processing the plurality of first conductive layers in a staircase pattern;
a pillar extending in a stacking direction of the stacked body in the stacked body away from the staircase portion in a first direction intersecting the stacking direction, the pillar forming a memory cell at an intersection with at least a part of each of the plurality of first conductive layers;
a contact disposed in the staircase portion and connected to one first conductive layer out of the plurality of first conductive layers;
a second insulating layer covering the staircase portion at least up to a height of an uppermost layer of the stacked body; and
a first layer disposed in the second insulating layer along a shape of the staircase portion, the first layer being of a type different from a type of at least the second insulating layer,
wherein:
the contact includes a second conductive layer extending from above the staircase portion to the one first conductive layer, the second conductive layer being integrated with the one first conductive layer,
the contact includes a liner layer covering a side wall of the second conductive layer and extending to at least a position below the first layer,
the contact includes a metal-containing insulating layer interposed between the second conductive layer and the liner layer, the metal-containing insulating layer extending on an inner side of the second insulating layer in the stacking direction,
the metal-containing insulating layer penetrates the second insulating layer below the first layer,
the metal-containing insulating layer continuously extends from a side wall of the second conductive layer to an upper surface of the one first conductive layer excluding a connection surface with the contact,
the contact includes a third conductive layer interposed between the second conductive layer and the metal-containing insulating layer and extending on the inner side of the second insulating layer in the stacking direction, and
the third conductive layer penetrates the second insulating layer below the first layer.
2 . The semiconductor memory device according to claim 1 , wherein the liner layer is a layer having selectivity in dry etching against the first layer.
3 . The semiconductor memory device according to claim 2 , wherein the liner layer is a fourth insulating layer of a same type as the second insulating layer.
4 . The semiconductor memory device according to claim 1 , wherein the liner layer is a layer having selectivity in wet etching against the second insulating layer.
5 . The semiconductor memory device according to claim 4 wherein the liner layer is a fourth conductive layer containing metal.
6 . The semiconductor memory device according to claim 1 , wherein the third conductive layer continuously extends on an inner side of the metal-containing insulating layer from a side wall of the second conductive layer to the upper surface of the one first conductive layer excluding the connection surface with the contact.