Three-dimensional memory device containing through-memory-level contact via structures
A first alternating stack of first insulating layers and first sacrificial material layers is formed with a first stepped surfaces located in a staircase region. A second alternating stack of second insulating layers and second sacrificial material layers with second stepped surfaces is formed over the first alternating stack. Areas of the second stepped surfaces overlap areas of the first stepped surfaces to reduce the size of the staircase region. The sacrificial material layers are subsequently replaced with electrically conductive layers. Laterally-insulated staircase region via structures contacting a respective one of the electrically conductive layers may be provided by forming stepped via cavities such that an annular surface of a respective sacrificial material layer is physically exposed at an annular step of the stepped via cavities. Laterally-insulated staircase region via structures may be formed in the stepped via cavities tot provide electrical connections to the electrically conductive layers.
1. A device structure comprising:
a first alternating stack of first insulating layers and first electrically conductive layers located over a substrate and including first stepped surfaces in a staircase region;
a first retro-stepped dielectric material portion overlying the first stepped surfaces of the first alternating stack;
a second alternating stack of second insulating layers and second electrically conductive layers located over the first alternating stack and including second stepped surfaces in the staircase region;
a second retro-stepped dielectric material portion overlying the second stepped surfaces of the second alternating stack;
a first laterally-insulated staircase region via structure vertically extending through, and contacting, a first subset of the second insulating layers of the second alternating stack, the first retro-stepped dielectric material portion, and a first subset of the first insulating layers of the first alternating stack; and
a second laterally-insulated staircase region via structure vertically extending through, and contacting, the first retro-stepped dielectric material portion and a second subset of the first insulating layers of the first alternating stack,
wherein:
the first laterally-insulated staircase region via structure comprises a first conductive via structure that is electrically connected to one of the second electrically conductive layers, and is electrically isolated from each of the first electrically conductive layers;
the second laterally-insulated staircase region via structure comprises a second conductive via structure that is electrically connected to one of the first electrically conductive layers;
a topmost surface of the second laterally-insulated staircase region via structure underlies the second alternating stack;
the one of the first electrically conductive layers comprises a metallic nitride liner formed around a metal fill portion;
the second conductive via structure comprises a contact via metallic liner formed around a contact via metal fill portion;
an annular horizontal surface of the metallic nitride liner contacts an annular horizontal surface of the contact via metallic liner; and
a concave cylindrical surface of the metallic nitride liner contacts a convex cylindrical surface of the contact via metallic liner.
2. The device structure of claim 1 , wherein areas of horizontal surfaces of the second stepped surfaces overlap with areas of horizontal surfaces of the first stepped surfaces in a plan view along a direction that is perpendicular to parallel horizontal surfaces of the first insulating layers, the first electrically conductive layers, the second insulating layers, and the second electrically conductive layers.
3. The device structure of claim 2 , wherein vertical surfaces of the second stepped surfaces are laterally offset relative to vertical surfaces of the first stepped surfaces along a horizontal direction that is perpendicular to a horizontal direction along which the vertical surfaces of the second stepped surfaces laterally extend.
4. The device structure of claim 1 , further comprising a lower-level metal interconnect structure formed within a lower-level dielectric material layer that is located between the substrate and the first alternating stack, wherein a bottom surface of the first conductive via structure contacts the lower-level metal interconnect structure.
5. The device structure of claim 1 , wherein the first conductive via structure comprises:
an upper conductive via portion extending through the second retro-stepped dielectric material portion and overlying the one of the second electrically conductive layers; and
a lower conductive via portion extending from a level of the one of the second electrically conductive layers at least to a bottommost layer of the first alternating stack and having a lesser lateral extent than the upper conductive via portion.
6. The device structure of claim 5 , wherein the first laterally-insulated staircase region via structure comprises:
an upper dielectric liner laterally surrounding the upper conductive via portion and contacting a sidewall of the second retro-stepped dielectric material portion; and
a lower dielectric liner laterally surrounding the lower conducive via portion and contacting the first subset of the second insulating layers of the second alternating stack, a portion of the first retro-stepped dielectric material portion, and the first subset of the first insulating layers of the first alternating stack, wherein the lower dielectric liner is disjoined from the upper dielectric liner.
7. The device structure of claim 1 , further comprising a second laterally-insulated staircase region via structure vertically extending through, and contacting, the second retro-stepped dielectric material portion, a second subset of the second insulating layers of the second alternating stack, the first retro-stepped dielectric material portion, and the second subset of the first insulating layers of the first alternating stack,
wherein the second conductive via structure is electrically isolated from each of the second electrically conductive layers.
8. The device structure of claim 7 , wherein a topmost surface of the first laterally-insulated staircase region via structure and a topmost surface of the second laterally-insulated staircase region via structure are located within a same horizontal plane.
9. The device structure of claim 1 , wherein:
each of the second conductive via structure and the one of the first electrically conductive layers comprises a respective portion of a metallic nitride liner that continuously extends across the second conductive via structure and the one of the first electrically conductive layers with a homogeneous material composition throughout; and
each of the second conductive via structure and the one of the first electrically conductive layers comprises a respective portion of a metallic fill material that is formed within the metallic nitride liner.
10. A device structure comprising:
a first alternating stack of first insulating layers and first electrically conductive layers located over a substrate and including first stepped surfaces in a staircase region;
a first retro-stepped dielectric material portion overlying the first stepped surfaces of the first alternating stack;
a second alternating stack of second insulating layers and second electrically conductive layers located over the first alternating stack and including second stepped surfaces in the staircase region;
a second retro-stepped dielectric material portion overlying the second stepped surfaces of the second alternating stack;
a first laterally-insulated staircase region via structure vertically extending through, and contacting, a first subset of the second insulating layers of the second alternating stack, the first retro-stepped dielectric material portion, and a first subset of the first insulating layers of the first alternating stack; and
a second laterally-insulated staircase region via structure vertically extending through, and contacting, the first retro-stepped dielectric material portion and a second subset of the first insulating layers of the first alternating stack,
wherein:
the first laterally-insulated staircase region via structure comprises a first conductive via structure that is electrically connected to one of the second electrically conductive layers, and is electrically isolated from each of the first electrically conductive layers;
the second laterally-insulated staircase region via structure comprises a second conductive via structure that is electrically connected to one of the first electrically conductive layers;
a topmost surface of the second laterally-insulated staircase region via structure underlies the second alternating stack;
each of the second conductive via structure and the one of the first electrically conductive layers comprises a respective portion of a metallic nitride liner that continuously extends across the second conductive via structure and the one of the first electrically conductive layers with a homogeneous material composition throughout; and
each of the second conductive via structure and the one of the first electrically conductive layers comprises a respective portion of a metallic fill material that is formed within the metallic nitride liner.
11. The device structure of claim 10 , wherein areas of horizontal surfaces of the second stepped surfaces overlap with areas of horizontal surfaces of the first stepped surfaces in a plan view along a direction that is perpendicular to parallel horizontal surfaces of the first insulating layers, the first electrically conductive layers, the second insulating layers, and the second electrically conductive layers.
12. The device structure of claim 11 , wherein vertical surfaces of the second stepped surfaces are laterally offset relative to vertical surfaces of the first stepped surfaces along a horizontal direction that is perpendicular to a horizontal direction along which the vertical surfaces of the second stepped surfaces laterally extend.
13. The device structure of claim 10 , further comprising a lower-level metal interconnect structure formed within a lower-level dielectric material layer that is located between the substrate and the first alternating stack, wherein a bottom surface of the first conductive via structure contacts the lower-level metal interconnect structure.
14. The device structure of claim 10 , wherein the first conductive via structure comprises:
an upper conductive via portion extending through the second retro-stepped dielectric material portion and overlying the one of the second electrically conductive layers; and
a lower conductive via portion extending from a level of the one of the second electrically conductive layers at least to a bottommost layer of the first alternating stack and having a lesser lateral extent than the upper conductive via portion.
15. The device structure of claim 14 , wherein the first laterally-insulated staircase region via structure comprises:
an upper dielectric liner laterally surrounding the upper conductive via portion and contacting a sidewall of the second retro-stepped dielectric material portion; and
a lower dielectric liner laterally surrounding the lower conducive via portion and contacting the first subset of the second insulating layers of the second alternating stack, a portion of the first retro-stepped dielectric material portion, and the first subset of the first insulating layers of the first alternating stack, wherein the lower dielectric liner is disjoined from the upper dielectric liner.
16. The device structure of claim 10 , further comprising a second laterally-insulated staircase region via structure vertically extending through, and contacting, the second retro-stepped dielectric material portion, a second subset of the second insulating layers of the second alternating stack, the first retro-stepped dielectric material portion, and the second subset of the first insulating layers of the first alternating stack,
wherein the second conductive via structure is electrically isolated from each of the second electrically conductive layers.
17. The device structure of claim 16 , wherein a topmost surface of the first laterally-insulated staircase region via structure and a topmost surface of the second laterally-insulated staircase region via structure are located within a same horizontal plane.
18. The device structure of claim 10 , wherein the one of the first electrically conductive layers comprises a metallic nitride liner formed around a metal fill portion.
19. The device structure of claim 18 , wherein the second conductive via structure comprises a contact via metallic liner formed around a contact via metal fill portion.
20. The device structure of claim 19 , wherein an annular horizontal surface of the metallic nitride liner contacts an annular horizontal surface of the contact via metallic liner.