Microelectronic devices including staircase structures, and related memory devices, electronic systems, and methods

1. A microelectronic device, comprising:

a stack structure overlying a source tier, the stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers;

a staircase structure within the stack structure and having steps comprising lateral edges of the tiers;

conductive contacts within a horizontal area of the staircase structure and vertically extending through the stack structure to the source tier; and

strapping structures laterally adjacent to the conductive contacts and having upper surfaces substantially coplanar with upper surfaces of the conductive contacts, each of the strapping structures in contact with one of the conductive contacts and with one of the conductive structures of the stack structure at one of the steps of the staircase structure.

2. The microelectronic device of claim 1 , wherein each of the strapping structures physically contact the one of the conductive structures of the stack structure on a lateral side and on a vertical side.

3. The microelectronic device of claim 1 , wherein:

the conductive contacts comprise conductive material at least partially laterally surrounded by a liner material; and

the strapping structures are coupled to upper portions of the conductive material of the conductive contacts and are physically separated from lower portions of the conductive material of the conductive contacts by the liner material.

4. The microelectronic device of claim 1 , wherein the conductive contacts vertically extend through the stack structure from an upper surface of the stack structure to conductive features within the source tier.

5. The microelectronic device of claim 1 , wherein:

each of the conductive contacts exhibits substantially the same vertical height; and

the steps of the staircase structure are free of additional conductive contacts terminating thereon.

6. The microelectronic device of claim 1 , wherein the strapping structures substantially laterally surround and physically contact upper portions of the conductive contacts above an elevational level of individual steps of the staircase structure, without being laterally adjacent and in physical contact with lower portions of the conductive contacts within the stack structure.

7. The microelectronic device of claim 1 , further comprising at least one dielectric material overlying the stack structure, wherein conductive portions of the conductive contacts physically contact the strapping structures along a vertical extent of upper portions of the conductive contacts laterally adjacent to the at least one dielectric material.

8. A memory device, comprising:

a stack structure comprising conductive structures vertically interleaved with insulative structures;

strings of memory cells vertically extending through the stack structure;

a staircase structure within the stack structure and having steps defined by lateral ends of the conductive structures and the insulative structures; and

conductive contact structures vertically extending through the stack structure, each of the conductive contact structures individually comprising:

an inner conductive core vertically extending from an uppermost boundary of the stack structure to conductive material underlying a lowermost boundary of the stack structure; and

an outer conductive shell laterally surrounding portions of the inner conductive core and in physical contact with one of the conductive structures of the stack structure at an elevational level of one of the steps of the staircase structure.

9. The memory device of claim 8 , further comprising insulative material laterally intervening between lower portions of the inner conductive core and the outer conductive shell of each of the conductive contact structures, an upper portion of the outer conductive shell overlying the insulative material and physically contacting the inner conductive core.

10. The memory device of claim 8 , wherein the outer conductive shell of each of the conductive contact structures is in physical contact with the one of the conductive structures of the stack structure on at least two consecutive sides thereof.

11. The memory device of claim 8 , further comprising isolation regions individually laterally separating the inner conductive core of one of the conductive contact structures from additional conductive structures below individual steps of the stack structure, wherein a lateral dimension of the outer conductive shell of the one of the conductive contact structures is relatively greater than a lateral dimension of one of the isolation regions most proximate thereto.

12. The memory device of claim 8 , further comprising an insulative liner material overlying the steps of the staircase structure, a width of the outer conductive shell of each of the conductive contact structures laterally adjacent to the insulative liner material relatively larger than an additional width of the outer conductive shell laterally adjacent to the one of the conductive structures of the stack structure.

13. An electronic system, comprising:

a processor operably coupled to an input device and an output device; and

a memory device operably coupled to the processor, the memory device comprising:

a stack structure comprising dielectric materials and conductive materials vertically alternating with the dielectric materials;

conductive contacts vertically extending through the stack structure from an uppermost boundary of the stack structure to conductive routing structures underlying a lowermost boundary of the stack structure; and

conductive structures substantially surrounding upper portions of the conductive contacts, at least some of the conductive materials of the stack structure in electrical communication with at least some of the conductive routing structures through the conductive contacts and the conductive structures.