Three-dimensional memory device containing through-memory-level contact via structures and method of making the same

1. A method of forming a device structure, comprising:

forming an alternating stack of insulating layers and sacrificial material layers including stepped surfaces in a staircase region over a substrate;

forming a retro-stepped dielectric material portion over the stepped surfaces of the alternating stack;

forming sacrificial via fill structures through the retro-stepped dielectric material portion and the alternating stack, each of the sacrificial via fill structures comprising a respective insulating liner that is a single continuous structure contacting a top surface of only one respective sacrificial material layer of the sacrificial material layers, a sidewall of a respective opening through the retro-stepped dielectric material portion, and a sidewall of a bottommost one of the sacrificial material layers;

replacing the sacrificial material layers with electrically conductive layers while each of the insulating liners are present within the sacrificial via fill structures; and

replacing the sacrificial via fill structures with laterally-insulated via structures, wherein each of the laterally-insulated via structures comprises a conductive via structure contacting an annular area of a top surface of a respective one of the electrically conductive layers.

2. The method of claim 1 , further comprising:

forming a patterning film over the retro-stepped dielectric material portion and the alternating stack; and

forming contact via openings by anisotropically etching through the patterning film and the retro-stepped dielectric material portion, wherein each of the contact via openings has a respective bottommost surface that coincides with a top surface of a respective one of the sacrificial material layers, and the top surfaces of the sacrificial material layers are physically exposed as the bottommost surfaces of the contact via openings, and wherein volumes of the contact via openings are subsequently filled with portions of the sacrificial via fill structures.

3. The method of claim 2 , further comprising:

forming sacrificial tubular liners at a periphery of each of the contact via openings; and

forming cylindrical via cavities by anisotropically etching through regions of the alternating stack that are not masked by the patterning film or the sacrificial tubular liners, wherein the sacrificial via fill structures are formed within volumes formed by removal of the sacrificial tubular liners and the cylindrical via cavities.

4. The method of claim 3 , further comprising:

depositing a continuous sacrificial liner material layer within the contact via openings and over the patterning film; and

anisotropically etching the continuous sacrificial liner material layer, wherein remaining portions of the continuous sacrificial liner material layer constitute the sacrificial tubular liners.

5. The method of claim 3 , wherein

the volumes formed by removal of the sacrificial tubular liners and volumes of the cylindrical via cavities collectively comprise two-tier via cavities;

each of the two-tier via cavities comprises an upper-tier volume extending through the retro-stepped dielectric material portion and a lower-tier volume extending through the respective one of the sacrificial material layers; and

wherein the sacrificial via fill structures are formed through the retro-stepped dielectric material portion and the alternating stack within volumes of the two-tier via cavities.

6. The method of claim 5 , wherein:

the lower-tier volume has a lesser lateral extent than the upper-tier volume;

the upper-tier volume overlies a physically exposed portion of a top surface of a respective one of the sacrificial material layers; and

a respective sidewall of the bottommost one of the sacrificial material layers is physically exposed to the lower-tier volume.

7. The method of claim 5 , further comprising forming lower-level metal interconnect structures embedded in lower-level dielectric material layers over the substrate, wherein:

the alternating stack is formed over the lower-level metal interconnect structures; and

a top surface of a respective one of the lower-level metal interconnect structures is physically exposed at a bottom of each of the two-tier via cavities.

8. The method of claim 5 , further comprising:

depositing an insulating liner layer in the two-tier via cavities;

depositing a sacrificial via fill material on the insulating liner layer; and

planarizing the sacrificial via fill material and portions of the insulating liner layer, wherein remaining portions of the sacrificial via fill material and the insulating liner layer constitute the sacrificial via fill structures.

9. The method of claim 8 , wherein:

the insulating layers comprise silicon oxide;

the sacrificial material layers comprise silicon nitride;

the insulating liner layer comprises silicon oxide; and

the sacrificial via fill material comprises a material selected from silicon nitride and a semiconductor material.

10. The method of claim 8 , wherein:

each of the insulating liners is a remaining portion of the insulating liner layer; and

each of the sacrificial via fill structures comprises a sacrificial via fill material portions is a remaining portion of the sacrificial via fill material; and

the method further comprises removing each sacrificial via fill material portion employing an isotropic etch process after replacing the sacrificial material layers with the electrically conductive layers.

11. The method of claim 10 , further comprising anisotropically etching the insulating liners, wherein each of the insulating liners is divided into an upper insulating spacer contacting a top surface of a respective one of the electrically conductive layers and a lower insulating spacer laterally surrounded by a bottommost one of the electrically conductive layers.

12. The method of claim 1 , further comprising forming memory stack structures through the alternating stack, wherein each of the memory stack structures comprises a vertical stack of charge storage elements, a tunneling dielectric layer laterally surrounded by the vertical stack of charge storage elements, and a vertical semiconductor channel laterally surrounded by the tunneling dielectric layer.

13. The method of claim 2 , wherein the bottommost surfaces of the contact via openings are vertically offset from each other.

14. The method of claim 2 , wherein the contact via openings do not extend through any of the sacrificial material layers or any of the insulating layers.

15. The method of claim 5 , wherein each of the two-tier cavities comprises:

a first sidewall that extends straight vertically from a top surface of the retro-stepped dielectric material portion to a top surface of a respective one of the sacrificial material layers; and

a second sidewall that extends straight vertically from the top surface of the respective one of the sacrificial material layers at least down to a bottom surface of a bottommost layer of the alternating stack.

16. The method of claim 15 , further comprising conformally depositing an insulating liner layer on each first sidewall, each second sidewall, and each physically exposed portion of the top surfaces of the sacrificial material layers.

17. The method of claim 16 , wherein the insulating liners are formed within the two-tier cavities, wherein each of the insulating liners comprises a respective portion of the insulating liner layer that is located within a respective one of the two-tier cavities, and wherein the sacrificial via fill structures are formed inside a respective one of the insulating liners.

18. The method of claim 17 , further comprising dividing each insulating liner into an upper insulating spacer and a lower spacer that do not contact each other, wherein the upper insulating spacer contacts a top surface of a respective one of the electrically conductive layers and the lower insulating spacer is laterally surrounded by a bottommost one of the electrically conductive layers and any additional electrically conductive layer, if any, located between the upper insulating spacer and the bottommost one of the electrically conductive layers.

19. The method of claim 18 , wherein each insulating liner is divided into the upper insulating spacer and the lower spacer by an anisotropic etch process that is performed after removal of the sacrificial via fill structures.

20. The method of claim 1 , wherein:

each of the sacrificial via fill structures comprises a combination of a sacrificial via fill material portion and the respective insulating liner;

each of the sacrificial via fill material portions is entirely removed after replacement of the sacrificial material layers with the electrically conductive layers;

each of the insulating liners is subsequently divided into an upper insulating spacer and a lower insulating spacer that are incorporated into a respective one of the laterally-insulated via structures; and

each of the laterally-insulated via structures comprises the upper insulating spacer and the lower insulating spacer.