Three-bit-per-cell programming using a four-bit-per-cell programming algorithm
An apparatus is provided that includes a plurality of memory cells, logic circuits coupled to the memory cells and configured to store 4-bit data in each of the memory cells, and a control circuit coupled to the memory cells and the logic circuits. The control circuit configured to cause the logic circuits to store 3-bit data in each of the memory cells.
1. An apparatus comprising:
a plurality of memory cells;
logic circuits coupled to the memory cells and configured to store 4-bit data in each of the memory cells using a 4-bit gray code; and
a control circuit coupled to the memory cells and the logic circuits, the control circuit configured to cause the logic circuits to use the 4-bit gray code to store only 3-bit data in each of the memory cells using fewer than sixteen possible threshold voltages.
2. The apparatus of claim 1 , wherein the logic circuits implement a first programming algorithm to program 4-bit data in each memory cell.
3. The apparatus of claim 2 , wherein the first programming algorithm comprises a 4-bit gray code.
4. The apparatus of claim 1 , wherein the logic circuits implement a second programming algorithm to program 3-bit data in each memory cell.
5. The apparatus of claim 1 , wherein the logic circuits implement a first programming algorithm that comprises 4-bit gray code, and wherein the logic circuits implement a second programming algorithm that comprises a 3-bit gray code based on the 4-bit gray code.
6. The apparatus of claim 1 , further comprising a plurality of data latches associated with each of the memory cells, wherein the control circuit is further configured to set a value of one of the data latches to 0 or 1 to store 3-bit data in each of the memory cells.
7. The apparatus of claim 1 , wherein each of the memory cells is configured to store 3 bits of data per memory cell and 4 bits of data per memory cell.
8. The apparatus of claim 1 , wherein the apparatus does not comprise separate logic circuits configured to store 3-bit data in each of the memory cells.
9. The apparatus of claim 1 , wherein the control circuit is further configured to tune verify levels to space a threshold voltage distribution of the memory cells.
10. The apparatus of claim 1 , further comprising four data latches associated with each of the memory cells, wherein data to be written to the memory cells are stored only in three of the four data latches.
11. A memory system comprising:
a memory die comprising a memory cell; and
a control circuit coupled to the memory cell, the control circuit configured to:
use a 4-bit gray code to program the memory cell to any of sixteen possible threshold voltages; and
use the 4-bit gray code to store 3-bit data in the memory cell using only eight of the sixteen possible threshold voltages.
12. The memory system of claim 11 , wherein the control circuit stores 3-bit data in the memory cell.
13. The memory system of claim 11 , wherein the control circuit comprises logic circuits configured to store 4-bit data or 3-bit data in the memory cell.
14. The memory system of claim 11 , wherein the control circuit comprises logic circuits that implement a first programming algorithm to program 4-bit data in the memory cell.
15. The memory system of claim 14 , wherein the first programming algorithm comprises a 4-bit gray code.
16. The memory system of claim 15 , wherein the logic circuits implement a second programming algorithm that comprises a 3-bit gray code based on the 4-bit gray code.
17. The memory system of claim 11 , further comprising a plurality of data latches associated with the memory cell, wherein the control circuit is further configured to set a value of one of the data latches to 0 or 1 to store 3-bit data in the memory cell.
18. The memory system of claim 11 , wherein the control circuit is further configured to tune verify levels to space a threshold voltage distribution of the memory cell.
19. A method comprising:
programming 3-bit data in a memory cell coupled to four data latches by:
storing the 3-bit data in a first, second and third of the four data latches;
forcing a value of a fourth one of the four data latches to 1 or 0; and
using a 4-bit gray code to program the 3-bit data in the memory cell.
20. The method of claim 19 , further comprising generating a 3-bit grey code from the 4-bit gray code.