Integrated standard cell structure

1. An integrated circuit, comprising:

a first standard cell having a first gate stack, a second gate stack, a first dielectric gate on a first standard cell boundary, and a second dielectric gate contacting the second gate stack;

a second standard cell having a third gate stack, a fourth gate stack, a third dielectric gate on a second standard cell boundary, and a fourth dielectric gate contacting the fourth gate stack;

a first continuous active region extending through the first standard cell and the second standard cell along a first direction; and

a second continuous active region extending through the first standard cell and the second standard cell along the first direction, wherein

the first standard cell adjoins the second standard cell on a fifth dielectric gate; and

each of the first gate stack, the third gate stack, the first dielectric gate, the first dielectric gate, the third dielectric gate, and the fifth dielectric gate is extending, along a second direction being orthogonal to the first direction, from the first continuous active region to the second continuous active region.

2. The integrated circuit of claim 1 , wherein

the first standard cell spans a first dimension D 1 along the first direction; and

the second standard cell spans a second dimension D 2 along the first direction, wherein D 2 =D 1 .

3. The integrated circuit of claim 1 , wherein

the second gate stack and the fourth dielectric gate are formed directly on the first continuous active region; and

the second dielectric gate and the fourth gate stack are formed directly on the second continuous active region.

4. The integrated circuit of claim 1 , wherein

the second gate stack and the fourth gate stack are formed directly on the first continuous active region; and

the second dielectric gate and the fourth dielectric gate are formed directly on the second continuous active region.

5. The integrated circuit of claim 4 , wherein

the first continuous active region is enclosed in an n-type doped well; and

the second continuous active region is enclosed in a p-type doped well.

6. The integrated circuit of claim 4 , wherein

the first continuous active region is enclosed in a p-type doped well; and

the second continuous active region is enclosed in an n-type doped well.

7. The integrated circuit of claim 1 , wherein each of the first, second, third, and fourth gate stacks includes a gate dielectric layer and a gate electrode over the gate dielectric layer.

8. The integrated circuit of claim 1 , wherein

the first gate stack is interposed between the second gate stack and the first dielectric gate; and

the third gate stack is interposed between the fourth gate stack and the third dielectric gate.

9. An integrated circuit, comprising:

a first standard cell having a first gate stack, a second gate stack, a first dielectric gate on a first standard cell boundary, and a second dielectric gate contacting the second gate stack;

a second standard cell having a third gate stack, a fourth gate stack, a third dielectric gate on a second standard cell boundary, and a fourth dielectric gate contacting the fourth gate stack; and

a first filler cell disposed between the first and second standard cells, and spanning a one-pitch dimension P from a fifth dielectric gate and a sixth dielectric gate along a first direction, wherein

the first standard cell spans a first dimension D 1 from the first dielectric gate to the fifth dielectric gate along the first direction,

the second standard cell spans a second dimension D 2 from the third dielectric gate to the sixth dielectric gate along the first direction, and

D 2 =D 1 ≥3* P.

10. The integrated circuit of claim 9 , further comprising

a first continuous active region extending through the first standard cell and the second standard cell; and

a second continuous active region extending through the first standard cell and the second standard cell.

11. The integrated circuit of claim 10 , wherein each of the first gate stack, the third gate stack, the first dielectric gate, and the third dielectric gate is extending from the first continuous active region to the second continuous active region.

12. The integrated circuit of claim 10 , wherein

the second gate stack and the fourth dielectric gate are formed directly on the first continuous active region; and

the second dielectric gate and the fourth gate stack are formed directly on the second continuous active region.

13. The integrated circuit of claim 10 , wherein

the second gate stack and the fourth gate stack are formed directly on the first continuous active region; and

the second dielectric gate and the fourth dielectric gate are formed directly on the second continuous active region.

14. The integrated circuit of claim 13 , wherein

the first continuous active region is enclosed in an n-type doped well; and

the second continuous active region is enclosed in a p-type doped well.

15. The integrated circuit of claim 13 , wherein

the first continuous active region is enclosed in a p-type doped well; and

the second continuous active region is enclosed in an n-type doped well.

16. An integrated circuit, comprising:

a first standard cell having a first gate stack, a second gate stack, a first dielectric gate on a first standard cell boundary and a second dielectric gate contacting the second gate stack;

a second standard cell having a third gate stack, a fourth gate stack, a third dielectric gate on a second standard cell boundary, and a fourth dielectric gate contacting the fourth gate stack;

a first filler cell disposed between the first and second standard cells, and spanning from a fifth dielectric gate to a sixth dielectric gate;

a first continuous active region extending through the first standard cell, the first filler cell and the second standard cell; and

a second continuous active region extending through the first standard cell, the first filler cell and the second standard cell, wherein

the first filler cell adjoins the first standard cell on a fifth dielectric gate and adjoins the second standard cell on a sixth dielectric gate,

the second dielectric gate is disposed directly on the first continuous active region, and

the fourth dielectric gate is disposed directly on the second continuous active region.

17. The integrated circuit of claim 16 , wherein the first filler cell further including a seventh dielectric gate equally distanced from the fifth and sixth dielectric gates.

18. The integrated circuit of claim 17 , wherein each of the first and fourth gate stacks and each of the first, third, fifth, sixth and seventh dielectric gates are extending from the first continuous active region to the second continuous active region.

19. The integrated circuit of claim 18 , wherein the first and second continuous active regions extend from the first dielectric gate to the third dielectric gate along a first direction.

20. The integrated circuit of claim 19 , wherein

the first filler cell spans a two-pitch dimension 2*P from the fifth dielectric gate and the sixth dielectric gate along the first direction;

the first standard cell spans a first dimension D 1 from the first dielectric gate to the fifth dielectric gate along the first direction; and

the second standard cell spans a second dimension D 2 from the third dielectric gate to the sixth dielectric gate along the first direction, wherein D 2 =D 1 =3*P.