Integrated standard cell structure
View Patent ↗An integrated circuit includes a first standard cell having a first pFET and a first nFET integrated, and having a first dielectric gate on a first standard cell boundary. The integrated circuit further includes a second standard cell being adjacent to the first standard cell, having a second pFET and a second nFET integrated, and having a second dielectric gate on a second standard cell boundary. The integrated circuit also includes a first filler cell configured between the first and second standard cells, and spanning from the first dielectric gate to the second dielectric gate. The first pFET and the second pFET are formed on a first continuous active region. The first nFET and the second nFET are formed on a second continuous active region.
1. An integrated circuit, comprising:
a first standard cell having a first gate stack, a second gate stack, a first dielectric gate on a first standard cell boundary, a second dielectric gate on a second standard cell boundary, and a third dielectric gate contacting the second gate stack;
a second standard cell having a third gate stack, a fourth gate stack, a fourth dielectric gate on a third standard cell boundary, a fifth dielectric gate on a fourth standard cell boundary, and a sixth dielectric gate contacting the fourth gate stack;
a filler cell disposed between the first and second standard cells, and spanning from the second dielectric gate to the fifth dielectric gate;
a first active region continuously extending through the first standard cell, the filler cell and the second standard cell along a first direction; and
a second active region continuously extending through the first standard cell, the filler cell and the second standard cell along the first direction, wherein
gate stacks and dielectric gates are longitudinally oriented along a second direction perpendicular to the first direction,
the third dielectric gate is disposed directly on the first active region and distanced away from the second active region, and
the sixth dielectric gate is disposed directly on the second active region and distanced away from the first active region.
2. The integrated circuit of claim 1 , wherein the filler cell further includes a seventh dielectric gate equally distanced from the second and fifth dielectric gates.
3. The integrated circuit of claim 1 , wherein the gate stacks and the dielectric gates are evenly distributed with a periodic pitch P.
4. The integrated circuit of claim 3 , wherein
the filler cell spans a two-pitch dimension 2*P from the second dielectric gate and the fifth dielectric gate along the first direction;
the first standard cell spans a first dimension D 1 from the first dielectric gate to the second dielectric gate along the first direction; and
the second standard cell spans a second dimension D 2 from the fourth dielectric gate to the fifth dielectric gate along the first direction, wherein each of D 2 and D 1 is greater than 2P.
5. The integrated circuit of claim 4 , wherein D 2 =D 1 =3*P.
6. The integrated circuit of claim 1 , wherein each of the first and third gate stacks and each of the first, second, fourth, fifth and seventh dielectric gates are extending from the first active region to the second active region.
7. The integrated circuit of claim 1 , wherein
the third dielectric gate is aligned with the second gate stack along the second direction; and
the sixth dielectric gate is aligned with the fourth gate stack along the second direction.
8. An integrated circuit, comprising:
a first standard cell having a first gate stack, a second gate stack, a first dielectric gate on a first standard cell boundary, and a second dielectric gate contacting the second gate stack;
a second standard cell having a third gate stack, a fourth gate stack, a third dielectric gate on a second standard cell boundary, and a fourth dielectric gate contacting the fourth gate stack; and
a first and second active regions continuously extending through the first standard cell and the second standard cell along a first direction and being distanced from each other along a second direction perpendicular to the first direction, wherein
the first standard cell adjoins the second standard cell on a fifth dielectric gate,
each of the first gate stack, the third gate stack, the first dielectric gate, the first dielectric gate, the third dielectric gate, and the fifth dielectric gate is longitudinally orienting along the second direction and is extending from the first active region to the second active region,
the second gate stack and the second dielectric gate are aligned along the second direction, and
the fourth dielectric gate and the fourth gate stack are aligned along the second direction.
9. The integrated circuit of claim 8 , wherein
the second gate stack and the fourth dielectric gate are formed directly on the first active region and are distanced away from the second active region; and
the second dielectric gate and the fourth gate stack are formed directly on the second active region and are distanced away from the first active region.
10. The integrated circuit of claim 8 , wherein
the second gate stack and the fourth gate stack are formed directly on the first active region and are distanced away from the second active region; and
the second dielectric gate and the fourth dielectric gate are formed directly on the second continuous active region and are distanced away from the second active region.
11. The integrated circuit of claim 10 , wherein
the first active region is enclosed in an n-type doped well; and
the second active region is enclosed in a p-type doped well.
12. The integrated circuit of claim 10 , wherein
the first active region is enclosed in a p-type doped well; and
the second active region is enclosed in an n-type doped well.
13. The integrated circuit of claim 8 , wherein each of the first, second, third, and fourth gate stacks includes a gate dielectric layer and a gate electrode over the gate dielectric layer.
14. The integrated circuit of claim 8 , wherein
the first gate stack is interposed between the second gate stack and the first dielectric gate; and
the third gate stack is interposed between the fourth gate stack and the third dielectric gate.
15. The integrated circuit of claim 8 , wherein
the first standard cell spans a first dimension D 1 along the first direction; and
the second standard cell spans a second dimension D 2 along the first direction, wherein D 2 =D 1 .
16. An integrated circuit, comprising:
a first standard cell having a first gate stack, a second gate stack, a first dielectric gate on a first standard cell boundary, and a second dielectric gate contacting the second gate stack;
a second standard cell having a third gate stack, a fourth gate stack, a third dielectric gate on a second standard cell boundary, and a fourth dielectric gate contacting the fourth gate stack; and
a filler cell disposed between the first and second standard cells, and spanning a one-pitch dimension P from a fifth dielectric gate and a sixth dielectric gate along a first direction, wherein
the first standard cell spans a first dimension D 1 from the first dielectric gate to the fifth dielectric gate along the first direction,
the second standard cell spans a second dimension D 2 from the third dielectric gate to the sixth dielectric gate along the first direction, and D 2 =D 1 >P.
17. The integrated circuit of claim 16 , further comprising
a first active region extending through the first standard cell and the second standard cell; and
a second active region extending through the first standard cell and the second standard cell, wherein
the first active region is enclosed in a first doped well of a first doping type; and
the second active region is enclosed in a second doped well of a second doping type being opposite the first doping type.
18. The integrated circuit of claim 17 , wherein
each of the first gate stack, the third gate stack, the first dielectric gate, and the third dielectric gate is extending from the first active region to the second active region along a second direction being orthogonal to the first direction; and
D 2 =D 1 ≥3*P.
19. The integrated circuit of claim 17 , wherein
the second gate stack and the fourth dielectric gate are formed directly on the first active region and are distanced away from the second active region; and
the second dielectric gate and the fourth gate stack are formed directly on the second active region and are distanced away from the first active region.
20. The integrated circuit of claim 17 , wherein
the second gate stack and the fourth gate stack are formed directly on the first active region;
the second dielectric gate and the fourth dielectric gate are formed directly on the second active region;
the second gate stack and the second dielectric gate are aligned along the second direction; and
the fourth gate stack and the fourth dielectric gate are aligned along the second direction.