Substrate having one or more electrical interconnects
An electronic device may include an integrated circuit, for instance a semiconductor die. The electronic device may include a substrate having a first layer and a second layer. The first and second layers may include interconnects recessed below a surface of the substrate. The substrate may include a passivation layer directly coupled with portions of the interconnects. A solder resist material may at least partially cover portions of the passivation layer directly coupled with the first interconnect surface.
1 . A substrate for an electronic device, the substrate comprising:
a first layer including a first interconnect and a first material, the first layer having a first layer surface and the first interconnect is recessed with respect to the first layer surface, wherein the first interconnect comprises a first interconnect surface and a first side surface adjacent the first interconnect surface;
a second layer directly coupled with the first interconnect surface, the first side surface adjacent the first interconnect surface, and the first material;
a third layer directly coupled with first interconnect surface and the second layer;
a fourth layer including a second interconnect and the first material, the fourth layer having a fourth layer surface and the second interconnect is recessed with respect to the fourth layer surface;
a fifth layer directly coupled with a second interconnect surface, a second side surface adjacent the second interconnect surface, and the first material; and
a sixth layer directly coupled with the second interconnect surface and the fifth layer;
wherein the first material at least partially covers portions of the second layer directly coupled with the first interconnect surface,
wherein the first material comprises carbon and oxygen, and
wherein the second layer comprises silicon and nitrogen.
2 . The substrate of claim 1 , wherein:
the first material comprises a solder resist material,
the second layer comprises a passivation layer, and
the third layer comprises a surface finish layer.
3 . The substrate of claim 1 , wherein:
the first material is spaced from portions of the fifth layer directly coupled with the second interconnect surface and the second side surface adjacent the second interconnect surface.
4 . The substrate of claim 3 , wherein:
the first interconnect has a first interconnect dimension, and
the second interconnect has a second interconnect dimension greater than the first interconnect dimension.
5 . The substrate of claim 3 , further comprising:
a first solder ball coupled with the third layer and the first material; and
a second solder ball coupled with the sixth layer and the first material, wherein the second solder ball is between the first material and a second side surface adjacent the second interconnect surface.
6 . The substrate of claim 3 , wherein:
the first material comprises a solder resist material,
the second layer comprises a first passivation layer,
the third layer comprises a first surface finish layer,
the fifth layer comprises a second passivation layer, and
the sixth layer comprises a second surface finish layer.
7 . The substrate of claim 1 , wherein the first material at least partially covers portions of the third layer directly coupled with the first interconnect surface.
8 . The substrate of claim 1 , wherein the second layer includes one or more of a silicon nitride compound material or a photoimageable dielectric material.
9 . The substrate of claim 1 , wherein:
the first material at least partially covers portions of the fifth layer directly coupled with the first interconnect surface.
10 . The substrate of claim 1 , further comprising a die coupled with the first interconnect of the substrate, and the substrate is a first-level interconnect for the die.
11 . The substrate of claim 1 , wherein:
the third layer is to couple with a first solder ball, and
the sixth layer is to couple with a second solder ball.
12 . A substrate for an electronic device, the substrate comprising:
a substrate core having a first side and a second side;
a first layer coupled with the first side of the substrate core, wherein:
the first layer includes a first interconnect and a first material,
the first interconnect comprises a first interconnect surface and a first side surface adjacent the first interconnect surface,
the first layer includes a second layer in contact with the first interconnect surface, the first side surface adjacent the first interconnect surface, and the first material, and
the first material at least partially covers a portion of the second layer; and
a third layer coupled with the second side of the substrate core, wherein:
the third layer includes a second interconnect and the first material,
the third layer includes a fourth layer coplanar with a portion of the second interconnect and in contact with the first material,
the fourth layer is spaced from the second interconnect, and
the first material is spaced from the second interconnect.
13 . The substrate of claim 12 , wherein the first material is located between the second interconnect and the fourth layer.
14 . The substrate of claim 13 , further comprising:
a fifth layer directly coupled with a second interconnect surface of the second interconnect; and
a solder ball directly coupled with the fifth layer and the first material.
15 . The substrate of claim 12 , wherein the fourth layer includes one or more of a silicon nitride compound material or a photoimageable dielectric material.
16 . The substrate of claim 12 , further comprising a die coupled with the first interconnect of the substrate, and the substrate is a first-level interconnect for the die.
17 . The substrate of claim 12 , wherein the portion of the second layer is a portion of the second layer in contact with the first interconnect surface.
18 . A substrate for an electronic device, the substrate comprising:
a first layer including a first interconnect and a first material, the first layer having a first layer surface and the first interconnect is recessed with respect to the first layer surface, wherein the first interconnect comprises a first interconnect surface and a first side surface adjacent the first interconnect surface;
a second layer coupled with the first interconnect surface, the first side surface adjacent the first interconnect surface, and the first material;
a third layer coupled with first interconnect surface and the second layer;
a fourth layer including a second interconnect and the first material, the fourth layer having a fourth layer surface and the second interconnect is recessed with respect to the fourth layer surface;
a fifth layer coupled with a second interconnect surface, a second side surface adjacent the second interconnect surface, and the first material; and
a sixth layer coupled with the second interconnect surface and the fifth layer;
wherein the first material at least partially covers portions of the second layer coupled with the first interconnect surface,
wherein the first material comprises carbon and oxygen, and
wherein the second layer comprises silicon and nitrogen.
19 . The substrate of claim 18 , wherein:
the first material is spaced from portions of the fifth layer coupled with the second interconnect surface and the second side surface adjacent the second interconnect surface.
20 . The substrate of claim 18 , wherein:
the first material at least partially covers portions of the fifth layer coupled with the first interconnect surface.
21 . The substrate of claim 20 , wherein:
the second layer is directly coupled with the first interconnect surface, the first side surface adjacent the first interconnect surface, and the first material,
the third layer is directly coupled with first interconnect surface and the second layer,
the fifth layer is directly coupled with a second interconnect surface, a second side surface adjacent the second interconnect surface, and the first material, and
the sixth layer is directly coupled with the second interconnect surface and the fifth layer.
22 . The substrate of claim 21 , wherein:
the third layer is to couple with a first solder ball, and
the sixth layer is to couple with a second solder ball.
23 . The substrate of claim 18 , wherein:
the second layer is directly coupled with the first interconnect surface, the first side surface adjacent the first interconnect surface, and the first material,
the third layer is directly coupled with first interconnect surface and the second layer,
the fifth layer is directly coupled with a second interconnect surface, a second side surface adjacent the second interconnect surface, and the first material, and
the sixth layer is directly coupled with the second interconnect surface and the fifth layer.
24 . A substrate for an electronic device, the substrate comprising:
a first layer including a first interconnect and a first material, the first layer having a first layer surface and the first interconnect is recessed with respect to the first layer surface, wherein the first interconnect comprises a first interconnect surface and a first side surface adjacent the first interconnect surface;
a second layer directly coupled with the first interconnect surface, the first side surface adjacent the first interconnect surface, and the first material;
a third layer directly coupled with first interconnect surface and the second layer, the third layer configured for coupling with a first solder ball;
a fourth layer having a fourth layer surface, wherein:
the fourth layer includes a second interconnect and the first material;
the second interconnect is recessed with respect to the fourth layer surface;
a fifth layer coplanar with a portion of the second interconnect and directly coupled with the first material, wherein the fifth layer is spaced from the second interconnect; and
a sixth layer directly coupled with the second interconnect surface, the sixth layer configured for coupling with a second solder ball;
wherein the first material is spaced from the second interconnect,
wherein the first material at least partially covers portions of the second layer directly coupled with the first interconnect surface,
wherein the first material comprises carbon and oxygen, and
wherein the second layer comprises silicon and nitrogen.
25 . The substrate of claim 24 , wherein the first material is between the second interconnect and the fifth layer.
26 . The substrate of claim 25 , further comprising the second solder ball, and the second solder ball is directly coupled with the sixth layer and the first material.
27 . The substrate of claim 25 , further comprising one or more electrical routing traces included in the first layer, and the second layer is coupled with the one or more electrical traces.
28 . A substrate for an electronic device, the substrate comprising:
a first layer including a first interconnect and a first material, the first layer having a first layer surface and the first interconnect is recessed with respect to the first layer surface, wherein the first interconnect comprises a first interconnect surface and a first side surface adjacent the first interconnect surface;
a second layer directly coupled with the first interconnect surface, the first side surface adjacent the first interconnect surface, and the first material; and
a third layer directly coupled with first interconnect surface and the second layer, the third layer configured for coupling with a first solder ball,
wherein the first material at least partially covers portions of the second layer directly coupled with the first interconnect surface,
wherein the first material at least partially covers portions of the third layer directly coupled with the first interconnect surface, and
wherein the second layer comprises silicon and nitrogen.
29 . The substrate of claim 28 , wherein the first material comprises carbon and oxygen.
30 . The substrate of claim 28 , further comprising:
a fourth layer including a second interconnect and the first material, the fourth layer having a fourth layer surface and the second interconnect is recessed with respect to the fourth layer surface;
a fifth layer directly coupled with a second interconnect surface, a second side surface adjacent the second interconnect surface, and the first material; and
a sixth layer directly coupled with the second interconnect surface and the fifth layer, the sixth layer configured for coupling with a second solder ball.
31 . The substrate of claim 30 , wherein the first material is spaced from portions of the fifth layer directly coupled with the second interconnect surface and the second side surface adjacent the second interconnect surface.