Build up material architecture for microelectronic package device
Microelectronic integrated circuit package structures include a first layer over a substrate, the first layer having a matrix material and a filler material within the matrix material. A second layer is on the first layer, the second layer comprising the matrix material or a second material, where the filler material is substantially absent from the second layer. A first portion of a conductive feature is on the second layer and a second portion of the conductive feature is on a sidewall of the first layer.
1 . An integrated circuit (IC) package structure, comprising:
a first layer over a substrate, the first layer comprising a matrix material and a filler material within the matrix material;
a second layer on the first layer, the second layer comprising the matrix material or a second material, wherein the filler material is substantially absent from the second layer; and
a conductive feature, wherein a first portion of the conductive feature is directly on the second layer and a second portion of the conductive feature is directly on a sidewall of the first layer.
2 . The IC package structure of claim 1 , wherein a thickness of the second layer is between about 500 nm and 1.5 microns.
3 . The IC package structure of claim 1 , wherein the filler material comprises a plurality of silica particles.
4 . The IC package structure of claim 1 , wherein the second layer comprises an organic polymer material.
5 . The IC package structure of claim 1 , wherein the second layer comprises a polyethylene teraphthalate (PET) layer.
6 . The IC package structure of claim 1 , wherein the first portion of the conductive feature is a trace, and the second portion is a via, and wherein the second layer is in contact with one or more particles of the filler material.
7 . The IC package structure of claim 6 , wherein the trace comprises copper, wherein a surface roughness of the copper trace is less than about 1100 nm.
8 . The IC package structure of claim 6 , wherein the via comprises copper, wherein a surface roughness of the copper via is greater than a roughness of the copper trace.
9 . A microelectronic package structure, comprising:
a first layer over a substrate, the first layer comprising a matrix material and a filler material within the matrix material;
a second layer on the first layer, the second layer comprising the matrix material or a material different from the matrix material, wherein the second layer is substantially free of the filler material;
a conductive feature, wherein a portion of the conductive feature is directly on the first layer;
a die coupled to the conductive feature and on the first layer; and
a power supply coupled to the die.
10 . The package structure of claim 9 , wherein the first layer comprises a first build up layer, and an additional build up layer is on the first build up layer.
11 . The package structure of claim 10 , wherein the second layer comprises a first second layer, and an additional second layer is between the first build up layer and the additional build up layer.
12 . The package structure of claim 10 , wherein the portion of the conductive feature on the second layer comprises a trace, and a second portion of the conductive feature comprises a via.
13 . The package structure of claim 10 , further comprising a board on a first side of the build up layer, wherein the die is over a second side of the build up layer, and wherein the die is electrically coupled to the board.
14 . The package structure of claim 9 , wherein the second layer comprises one or more of an epoxy phenol-based polyimide or a benzocyclobutene (BCB) material.
15 . The package structure of claim 9 , wherein a layer comprising an epoxy, a polyimide or a maleimide, or combinations thereof is on a first side of the conductive feature, on a side opposite of the second layer.