IP Library › Granted Patent US 12,456,630
Granted Patent B2
US 12,456,630 · App. 17/857,752 · Granted Oct 28, 2025

Method of manufacturing semiconductor structure having heat dissipation structure

Inventor: Shing-Yih Shih (New Taipei, TW)
Assignee: NANYA TECHNOLOGY CORPORATION
H01L21/4882H01L23/3677H01L23/3733H01L24/08H01L24/80H01L25/0657H01L23/3142H01L23/367H01L23/481H01L2224/08146H01L2224/80895H01L2224/80896H01L2225/06524H01L2225/06544H01L2225/06589H01L2924/35121
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Quick Facts
Patent No.
US 12,456,630
App. No.
17/857,752
Granted
Oct 28, 2025
Kind
B2
Abstract

A method of manufacturing a semiconductor structure is provided. The method includes forming a thermal conductive structure embedded within a first passivation layer of a first wafer, and forming a plurality of conductive vias penetrating a first substrate of the first wafer and in contact with the thermal conductive structure. The method further includes forming a first connecting structure in contact with the thermal conductive structure and exposed by a surface of the first passivation layer. The method further includes bonding the first connecting structure of the first wafer to a second connecting structure of a second wafer, and bonding the first passivation layer of the first wafer to a first dielectric layer of the second wafer, wherein a first seal ring embedded within the first dielectric layer of the second wafer is thermally connected to the thermal conductive structure through the first connecting structure and the second connecting structure.

Claims (43)

1. A method for manufacturing a semiconductor structure, comprising:

forming a thermal conductive structure embedded within a first passivation layer of a first wafer, wherein the thermal conductive structure is disposed between an upper surface and a lower surface of the first passivation layer;

forming a plurality of conductive vias penetrating a first substrate of the first wafer and in contact with the thermal conductive structure through the lower surface of the first passivation layer;

forming a first connecting structure in contact with the thermal conductive structure and exposed by the upper surface of the first passivation layer;

bonding the first connecting structure of the first wafer to a second connecting structure of a second wafer; and

bonding the first passivation layer of the first wafer to a first dielectric layer of the second wafer, wherein the first passivation layer is disposed between the first substrate and the first dielectric layer of the second wafer

wherein a first seal ring embedded within the first dielectric layer of the second wafer is thermally connected to the thermal conductive structure through the first connecting structure and the second connecting structure, and

wherein the first dielectric layer of the second wafer comprises a first circuit region and a second dielectric layer of the third wafer comprises a second circuit region, and wherein the first circuit region and the second circuit region are located on opposite sides of the second substrate.

2. The method of claim 1 , wherein each of the plurality of conductive vias comprising a first end embedded within the first passivation layer and a second end exposed by a surface of the first substrate.

3. The method of claim 1 , further comprising:

forming a second passivation layer on a second substrate of the second wafer;

forming a first conductive via penetrating the second passivation layer and the second substrate;

bonding the first conductive via of the second wafer to a third connecting structure of a third wafer; and

bonding a third passivation layer of the third wafer to the second passivation layer of the second wafer.

4. The method of claim 1 , wherein the first circuit region of the second wafer is electrically connected to the second circuit region of the third wafer through a fourth connecting structure embedded within the third passivation layer and a second conductive via penetrating the second substrate.

5. The method of claim 1 , wherein the thermal conductive structure comprises a mesh profile.

6. A method for manufacturing a semiconductor structure, comprising:

providing a first substrate;

forming a first passivation layer on the first substrate;

forming a first dielectric layer on the first passivation layer, wherein the first passivation layer is disposed between the first substrate and the first dielectric layer;

forming a second substrate on the first dielectric layer;

forming a first seal ring embedded within the first dielectric layer and surrounding a circuit region of the first dielectric layer;

forming a thermal conductive structure embedded within the first passivation layer, wherein the thermal conductive structure is disposed between an upper surface and a lower surface of the first passivation layer; and

forming a first conductive via embedded within the second substrate, wherein a first end of the first conductive via is exposed by a surface of the second substrate, and a second end of the first conductive via is in contact with the thermal conductive structure,

wherein the thermal conductive structure is connected with the first seal ring through a first connecting structure.

7. The method of claim 6 , further comprising: forming a second seal ring embedded within the first dielectric layer and surrounded by the first seal ring, wherein the second seal ring is connected to the first seal ring through a second connecting structure, the thermal conductive structure, and the first connecting structure.

8. The method of claim 6 , wherein forming the thermal conductive structure comprises:

forming a first rib extending in a first direction; and

forming a second rib spaced apart from the first rib and extending parallel with the first rib.

9. The method of claim 8 , wherein forming the thermal conductive structure further comprises:

forming a third rib extending in a second direction perpendicular to the first direction; and

forming a fourth rib spaced apart from the third rib and extending parallel with the third rib;

wherein the third rib intersects with the first rib and the second rib, and the fourth rib intersects with the first rib and the second rib.

10. The method of claim 8 , further comprising:

forming a first conductive via landing on the first rib; and

forming a second conductive via landing on the first rib;

wherein the first conductive via comprising an end exposed by a surface of the second substrate, and the second conductive via comprising an end exposed by the surface of the second substrate.

11. The method of claim 8 , further comprising:

forming a first conductive via landing on an intersection of the third rib and the first rib; and

forming a second conductive via landing on an intersection of the fourth rib and the first rib.

12. The method of claim 7 , further comprising: forming a third seal ring embedded within the first dielectric layer, wherein the third seal ring is spaced apart from the first seal ring, and wherein the third seal ring is further from the thermal conductive structure than the first seal ring.

13. The method of claim 12 , wherein the third seal ring is connected to the first seal ring through a third connecting structure, and the thermal conductive structure comprises a mesh profile.

14. The method of claim 12 , further comprising: forming a fourth seal ring embedded within the first dielectric layer and surrounded by the third seal ring, wherein the fourth seal ring is connected to the second seal ring through a fourth connecting structure.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2022
From: SHIH, SHING-YIH
To: NANYA TECHNOLOGY CORPORATION
Reel/Frame 060508/0027 →
Continuity (1)
Related Publication 20240014048A1 · Jan 11, 2024
References Cited (28)
US 9012811B2 · White · 2015 [cited by applicant]
US 9035445B2 · Lin · 2015 [cited by examiner]
US 9466575B2 · Tomita · 2016 [cited by examiner]
US 20050046002A1 · Lee · 2005 [cited by examiner]
US 20070170591A1 · Yamanoue et al. · 2007 [cited by applicant]
US 20090321890A1 · Jeng et al. · 2009 [cited by applicant]
US 20110215457A1 · Park · 2011 [cited by examiner]
US 20120112329A1 · Yen · 2012 [cited by examiner]
US 20150084164A1 · Tomita · 2015 [cited by applicant]
US 20190363079A1 · Thei et al. · 2019 [cited by applicant]
US 20200229294A1 · Thibado et al. · 2020 [cited by applicant]
US 20200312817A1 · Wu et al. · 2020 [cited by applicant]
US 20210305200A1 · Lin et al. · 2021 [cited by applicant]
US 20220013502A1 · Lee et al. · 2022 [cited by applicant]
US 20220037528A1 · Chuang · 2022 [cited by examiner]
US 20230021125A1 · Ohba · 2023 [cited by examiner]
US 20230062027A1 · Chang · 2023 [cited by examiner]
US 20230067714A1 · Chang et al. · 2023 [cited by applicant]
US 20230170249A1 · Chuang et al. · 2023 [cited by applicant]
US 20230352317A1 · Chuang · 2023 [cited by examiner]
CN 103178047B · 2018 [cited by applicant]
CN 116798986A · 2023 [cited by examiner]
JP 2002261455A · 2002 [cited by applicant]
KR 100537892B1 · 2005 [cited by examiner]
TW 200411902A · 2004 [cited by applicant]
TW 201327740A · 2013 [cited by applicant]
TW 202121618A · 2021 [cited by applicant]
WO WO2023206649A1 · 2023 [cited by examiner]