Granted Patent B2

US 12,568,833 · App. 17/810,026 · Granted Mar 3, 2026

Inventors: Takayuki Ohba (Tokyo, JP); Shinji Sugatani (Saitama, JP)

Assignees: TOKYO INSTITUTE OF TECHNOLOGY; ADVANTEST CORPORATION

H01L23/49838H01L23/49822

Abstract

Claims (29)

1 . A semiconductor device comprising:

a power supply and ground layer, the power supply and ground layer including a substrate and a wiring part;

a semiconductor chip disposed over the power supply and ground layer, the semiconductor chip including through-electrodes disposed inside the semiconductor chip; and

a first insulating layer extending between the semiconductor chip and the power supply and ground layer,

wherein the substrate has one or more grooves whose openings are directed toward the semiconductor chip, and the wiring part is disposed within the one or more grooves via a second insulating layer and is formed in a predetermined pattern,

wherein the substrate is connected to ground wiring of the semiconductor chip and the wiring part is connected to power supply wiring of the semiconductor chip,

wherein the wiring part is not exposed from a bottom portion of the substrate in a state in which the wiring part is covered by the bottom portion whose surface has been ground and polished such that the bottom portion of the substrate has a predetermined thickness, and

wherein the through-electrodes penetrate through the first insulating layer.

2 . The semiconductor device according to claim 1 , wherein the predetermined pattern is a mesh pattern in a plan view.

3 . The semiconductor device according to claim 2 , wherein the substrate has a side wall portion and a plurality of columnar portions, the side wall portion surrounding the bottom portion, and the columnar portions being disposed in a region on the bottom portion surrounded by the side wall portion while being spaced apart from each other, and

wherein the columnar portions are disposed within openings of the mesh pattern.

4 . The semiconductor device according to claim 1 , wherein a decoupling capacitor is formed by the substrate, the second insulating layer, and the wiring part.

5 . The semiconductor device according to claim 1 ,

wherein the substrate is connected to the ground wiring of the semiconductor chip and the wiring part is connected to the power supply wiring of the semiconductor chip by the through-electrodes, and

wherein a total area of end faces of through-electrodes connected to the substrate or to the wiring part is 2% or more of an area of a back surface of the semiconductor chip.

6 . The semiconductor device according to claim 1 , wherein the substrate is formed of silicon, and a volume of the silicon is 60% or less of a total volume of the silicon and the wiring part.

7 . The semiconductor device according to claim 6 , wherein the wiring part includes a metal layer.

8 . The semiconductor device according to claim 7 , wherein the metal layer is porous.

9 . The semiconductor device according to claim 6 , wherein the wiring part includes a metal layer and a carbon layer, the metal layer being located closer to the semiconductor chip, and the carbon layer being located under the metal layer.

10 . The semiconductor device according to claim 9 , wherein an area of the carbon layer is 10% or more of a total area of the carbon layer and the metal layer in a vertical sectional view.

11 . The semiconductor device according to claim 9 , wherein the carbon layer includes carbon nanotubes or graphene pieces, and the metal layer includes copper.

12 . The semiconductor device according to claim 1 , further comprising a connection wiring part that is disposed between the power supply and ground layer and the semiconductor chip and includes higher density wiring than wiring of the wiring part.

13 . The semiconductor device according to claim 1 , further comprising a connection wiring part that includes higher density wiring than wiring of the wiring part,

wherein the semiconductor chip includes a plurality of semiconductor chips disposed at different positions over the power supply and ground layer in a plan view,

wherein the connection wiring part is disposed between the power supply and ground layer and each of the semiconductor chips, and

wherein the semiconductor chips are connected to each other by the connection wiring part.

14 . The semiconductor device according to claim 1 , wherein the wiring part is divided into wiring parts of a plurality of systems in a plan view, the wiring parts being isolated from each other, and

wherein the wiring parts of the respective systems are connected to power supply wiring of different systems of the semiconductor chip.

15 . The semiconductor device according to claim 1 , wherein the power supply and ground layer is larger than the semiconductor chip in a plan view.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (11)