Integrated circuit packages and methods of forming the same
In an embodiment, a device includes: a first integrated circuit die; a second integrated circuit die bonded to the first integrated circuit die in a face-to-back manner; a dummy semiconductor feature adjacent the second integrated circuit die and bonded to the first integrated circuit die; a support substrate attached to the dummy semiconductor feature and the second integrated circuit die; and a passivation layer extending along a top surface of the support substrate, an outer sidewall of the dummy semiconductor feature, an outer sidewall of the first integrated circuit die, and a top surface of the first integrated circuit die.
1 . A method comprising:
forming a first gap-filling dielectric around a first integrated circuit die;
bonding a second integrated circuit die to the first integrated circuit die;
forming a liner around the second integrated circuit die;
forming a second gap-filling dielectric on the liner and around the second integrated circuit die, the first gap-filling dielectric and the second gap-filling dielectric comprising a first dielectric material, the liner comprising a second dielectric material, the second dielectric material being different from the first dielectric material;
attaching a support substrate to the second gap-filling dielectric and the second integrated circuit die;
removing the first gap-filling dielectric and the second gap-filling dielectric with a chemical process, wherein the chemical process comprises:
etching the first gap-filling dielectric with a first etch that selectively etches the first dielectric material at a faster rate than the second dielectric material;
etching the liner with a second etch that selectively etches the second dielectric material at a faster rate than the first dielectric material; and
etching the second gap-filling dielectric with a third etch that selectively etches the first dielectric material at a faster rate than the second dielectric material; and
singulating the support substrate with a mechanical process.
2 . The method of claim 1 , wherein the first dielectric material is silicon oxide and the second dielectric material is silicon nitride.
3 . The method of claim 1 , wherein the first etch and the third etch are wet etches, and the second etch is a dry etch.
4 . The method of claim 1 , further comprising:
forming an etch stop layer on the second gap-filling dielectric and the second integrated circuit die, the support substrate attached to the etch stop layer, the etch stop layer comprising the second dielectric material.
5 . The method of claim 1 , wherein the chemical process further comprises:
forming a mask covering the first integrated circuit die, the mask comprising an opening, wherein the first etch, the second etch, and the third etch each extend the opening.
6 . The method of claim 1 , wherein the mechanical process comprises:
sawing or cutting the support substrate.
7 . The method of claim 1 , further comprising:
after the chemical process and before the mechanical process, depositing a passivation layer on a top surface and along an outer sidewall of the first integrated circuit die.
8 . A method comprising:
forming a liner around an integrated circuit die;
forming a gap-filling dielectric on the liner and around the integrated circuit die, the gap-filling dielectric comprising a first dielectric material, the liner comprising a second dielectric material, the second dielectric material being different from the first dielectric material;
attaching a support substrate to the gap-filling dielectric and the integrated circuit die;
removing the gap-filling dielectric with a chemical process, wherein the chemical process comprises:
etching the gap-filling dielectric with a wet etch that selectively etches the first dielectric material at a faster rate than the second dielectric material; and
etching the liner with a dry etch that selectively etches the second dielectric material at a faster rate than the first dielectric material;
depositing a passivation layer on a top surface and an outer sidewall of the integrated circuit die; and
singulating the passivation layer and the support substrate with a mechanical process.
9 . The method of claim 8 , wherein the chemical process comprises:
forming a mask covering the integrated circuit die, the mask comprising an opening; and
extending the opening through the gap-filling dielectric with an etch.
10 . The method of claim 8 , wherein the mechanical process comprises:
sawing or cutting the passivation layer and the support substrate.
11 . A method comprising:
forming a first gap-filling dielectric around a first integrated circuit die;
bonding a second integrated circuit die to the first integrated circuit die;
forming a liner around the second integrated circuit die;
forming a second gap-filling dielectric on the liner and around the second integrated circuit die;
attaching a support substrate to the second gap-filling dielectric and the second integrated circuit die;
forming an opening by:
removing the first gap-filling dielectric with a first etch;
removing the liner with a second etch; and
removing the second gap-filling dielectric with a third etch, the second etch being different from the first etch and different from the third etch;
forming an epoxy material in the opening; and
singulating the epoxy material and the support substrate with a mechanical process.
12 . The method of claim 11 , wherein forming the epoxy material in the opening comprises molding a molding compound in the opening.
13 . The method of claim 11 , wherein forming the epoxy material in the opening comprises flowing an underfill in the opening.
14 . The method of claim 11 , further comprising:
depositing a passivation layer on a top surface of the epoxy material and on a top surface of the first integrated circuit die.
15 . The method of claim 14 , further comprising:
forming a die connector through the passivation layer, the die connector connected to the first integrated circuit die.
16 . The method of claim 11 , wherein the first etch and the third etch are wet etches, and the second etch is a dry etch.
17 . The method of claim 11 , wherein the first gap-filling dielectric and the second gap-filling dielectric comprise silicon oxide, and the liner comprises silicon nitride.
18 . The method of claim 17 , wherein the first etch and the third etch are performed with hydrofluoric acid, and the second etch is performed with carbon tetrafluoride.
19 . The method of claim 11 , wherein the first etch selectively etches the first gap-filling dielectric at a faster rate than the liner, the second etch selectively etches the liner at a faster rate than the second gap-filling dielectric, and the third etch selectively etches the second gap-filling dielectric at a faster rate than the liner.
20 . The method of claim 11 , further comprising:
forming a mask covering the first integrated circuit die and the second integrated circuit die, the mask having a pattern of the opening.