Semiconductor device with backside power rail and methods of fabrication thereof
A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first side and a second side opposing the first side, a source/drain epitaxial feature disposed adjacent the first side of the substrate, wherein the source/drain epitaxial feature comprises a first epitaxial layer, a second epitaxial layer in contact with the first epitaxial layer, and a third epitaxial layer having sidewalls surrounded by and in contact with the second epitaxial layer. The device structure also includes a first silicide layer in contact with the substrate, the first, second, and third epitaxial layers, a first source/drain contact extending through the substrate from the first side to the second side, and a first metal capping layer disposed between the first silicide layer and the first source/drain contact.
1 . A method for forming a semiconductor device structure, comprising:
depositing a sacrificial gate structure over a portion of a first fin structure and a second fin structures formed from a substrate, wherein each first and second fin structure comprises a sacrificial layer and a plurality of first semiconductor layers and a plurality of second semiconductor layers alternatingly stacked;
forming a source/drain feature between the first fin structure and the second fin structure, wherein the source/drain feature comprises a first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and a third epitaxial layer on the second epitaxial layer;
removing the sacrificial gate structure and the plurality of second semiconductor layers to expose portions of the plurality of first semiconductor layers of the first and second fin structures;
forming a gate electrode layer to surround at least the exposed portion of one of the plurality of first semiconductor layers of the first and second fin structures;
depositing a first silicide layer over a front side of the substrate, wherein the first silicide layer is in contact with the second and third epitaxial layers;
forming a front side source/drain contact and a front side source/drain contact via over the first silicide layer;
planarizing a backside of the substrate until the sacrificial layer is removed;
depositing a hard mask layer on the backside of the substrate;
forming a contact opening through the hard mask layer, the substrate, the first epitaxial layer, and the second epitaxial layer to expose the third epitaxial layer;
depositing a second silicide layer so that the second silicide layer is in contact with the substrate, the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer; and
forming a backside source/drain contact over the second silicide layer, wherein the backside source/drain contact is connected to a backside power rail.
2 . The method of claim 1 , further comprising:
prior to forming the source/drain feature, forming a facetted structure on exposed surfaces of the plurality of first semiconductor layers of the first and second fin structures.
3 . The method of claim 2 , wherein the first silicide layer has a first thickness and the second silicide layer has a second thickness less than the first thickness.
4 . The method of claim 1 , further comprising:
after forming the backside source/drain contact, forming a backside interlayer dielectric (ILD) layer over the backside source/drain contact and the hard mask layer, wherein the backside ILD layer electrically isolates the backside source/drain contact from adjacent structures.
5 . A method for forming a semiconductor device structure, comprising:
forming a source/drain feature within a region defined by a first side of a substrate, a first fin structure, and a second fin structure;
forming a contact etch stop layer (CESL) on the source/drain feature;
forming a first interlayer dielectric (ILD) layer on the CESL;
removing the first ILD layer and a portion of the CESL to expose the source/drain feature;
forming a first silicide layer on a first side of the source/drain feature, wherein the first silicide layer has a first thickness;
forming a first source/drain contact over the first silicide layer;
forming a back-end-of-line (BEOL) interconnect structure over the first source/drain contact;
forming a contact opening extending from a second side of the substrate to the first side of the substrate to expose a second side of the source/drain feature; and
after forming the contact opening, forming a second silicide layer on the second side of the source/drain feature, wherein the second silicide layer has a second thickness less than the first thickness; and
forming a second source/drain contact in the contact opening.
6 . The method of claim 5 , wherein the source/drain feature comprises:
a first epitaxial layer;
a second epitaxial layer in contact with the first epitaxial layer; and
a third epitaxial layer having sidewalls surrounded by and in contact with the second epitaxial layer.
7 . The method of claim 5 , wherein the second silicide layer is in further contact with the second epitaxial layer and the third epitaxial layer.
8 . The method of claim 5 , further comprising:
after forming the second silicide layer, forming a metal capping layer on the second silicide layer.
9 . The method of claim 5 , further comprising:
after forming the second source/drain contact, forming a second ILD layer over the second source/drain contact; and
forming a conductive feature in the second ILD layer, wherein the conductive feature is in electrical connection with a power supply.
10 . The method of claim 9 , wherein each first and second fin structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers alternatingly arranged.
11 . The method of claim 10 , further comprising:
after forming a first ILD layer on the CESL;
removing the plurality of second semiconductor layers in the first and second fin structures to expose portions of the plurality of first semiconductor layers; and
forming a gate electrode layer to surround the exposed portions of the plurality of first semiconductor layers in the first and second fin structures.
12 . The method of claim 5 , further comprising:
after forming the contact opening, depositing a barrier layer on sidewalls of the contact opening before forming the second source/drain contact, wherein the barrier layer is in contact with the substrate and the source/drain feature.
13 . A method for forming a semiconductor device structure, comprising:
forming a fin structure from a substrate, wherein the fin structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers alternatingly arranged;
forming a source/drain feature over a first side of the substrate, wherein the source/drain feature comprises:
a first epitaxial layer in contact with the first side of the substrate and a sidewall of at least one of the plurality of first semiconductor layer;
a second epitaxial layer in contact with the first epitaxial layer; and
a third epitaxial layer having sidewalls surrounded by and in contact with the second epitaxial layer;
removing the plurality of second semiconductor layers;
forming a gate electrode layer to surround a portion of each of the plurality of first semiconductor layers;
forming a first silicide layer on a first side of the source/drain feature, wherein the first silicide layer is in contact with the second and third epitaxial layers;
forming a first source/drain contact over the first silicide layer;
removing a portion of the substrate to expose a second side of the source/drain feature;
forming a second silicide layer on the second side of the source/drain feature; and
forming a second source/drain contact over the second silicide layer.
14 . The method of claim 13 , wherein the second silicide layer is formed to contact a portion of the first, second, and third epitaxial layers.
15 . The method of claim 14 , wherein the first silicide layer has a first thickness and the second silicide layer has a second thickness different than the first thickness.
16 . The method of claim 15 , wherein the second thickness is greater than the first thickness.
17 . The method of claim 15 , wherein the first silicide layer and the second silicide layer comprise the same material.
18 . The method of claim 13 , wherein the second source/drain contact is in electrical connection with a power supply.
19 . The method of claim 13 , wherein the first silicide layer is formed so that a portion contacting the third epitaxial layer has a first width, and a portion contacting the second epitaxial layer has a second width less than the first width.
20 . The method of claim 19 , wherein the first epitaxial layer is undoped, and wherein the second epitaxial layer has a first dopant concentration and the third epitaxial layer has a second dopant concentration greater than the first dopant concentration.