Memory array having connections going through control gates
Some embodiments include apparatuses and methods having a substrate, a memory cell string including a body, a select gate located in a level of the apparatus and along a portion of the body, and control gates located in other levels of the apparatus and along other respective portions of the body. At least one of such apparatuses includes a conductive connection coupling the select gate or one of the control gates to a component (e.g., transistor) in the substrate. The connection can include a portion going through a portion of at least one of the control gates.
1. A method comprising: forming a staircase structure exposing edges of a first control gate, a second control gate, and a select gate in different levels of a device over a substrate of the device;
forming an opening in an area of the device between an edge that is toward the staircase structure of the first control gate and an edge that is toward the staircase structure of the select gate or the second control gate; and
forming a connection coupling the one of the select gate and the second control gate to a conductive contact located between the substrate and the first control gate, wherein the connection is formed such that a portion of the connection is inside the opening.
2. The method of claim 1 , wherein the opening is formed such that a bottom of the opening is coupled to the conductive contact.
3. The method of claim 1 , wherein forming the opening includes:
removing material from part of the first control gate to form another opening through the first control gate;
filling the another opening with a dielectric material; and
forming the opening in the dielectric material, such that the opening is separated from remaining portions of the first control gate by a portion of the dielectric material.
4. The method of claim 3 , wherein forming the connection includes filling the opening with a conductive material.
5. The method of claim 1 , wherein forming the connection includes:
forming a first segment of the connection such that the first segment is coupled to one of the select gate and the second control gate and extends in a direction perpendicular to the substrate;
forming a second segment of the connection in the opening; and
forming a third segment to couple the first segment to the second segment.
6. A method comprising:
forming a stack of dielectric materials interleaved with conductive materials;
removing a portion of the dielectric materials and a portion of the conductive materials to form a staircase structure that includes respective edges of a remaining portion of the dielectric materials and respective edges of a remaining portion of the conductive materials, wherein one of the conductive materials of the remaining portion of the conductive materials forms a select gate associated with a memory cell string of a memory device;
forming an additional dielectric material over the staircase structure;
forming a first opening in the additional dielectric material adjacent to the select gate and between an edge that is toward the staircase structure of the select gate and an edge that is toward the staircase structure of a conductive material in the remaining portion of the conductive materials, wherein the first opening extends through of the remaining portion of the dielectric materials and the remaining portion of the conductive materials to expose a portion of a conductive contact located below the remaining portion of the dielectric materials and the remaining portion of the conductive materials;
forming a second opening in the additional dielectric material to expose a portion of the select gate; and
forming a connection to couple the portion of the select gate to the portion of the conductive contact.
7. The method of claim 6 , wherein forming the connection includes filling the first and second openings with a conductive material.
8. The method of claim 6 , wherein forming the connection includes:
forming a first segment of the connection in the first opening;
forming a second segment of the connection in the second opening; and
forming a third segment of the connection to couple the first segment to the second segment.
9. The method of claim 6 , wherein one of the conductive materials of the remaining portion of the conductive materials forms a control gate associated with the memory cell string, and a distance between a pillar of the memory cell string and the edge of the conductive material in the remaining portion of the conductive materials and an edge of the control gate is greater than a distance between the pillar and the edge of the select gate.
10. The method of claim 6 , further comprising:
forming a third opening in the additional dielectric material to expose a portion of the conductive material in the remaining portion of the conductive materials;
forming a fourth opening in the additional dielectric material to expose a portion of an additional conductive contact that is separated from the remaining portion of the conductive materials; and
forming an additional connection to couple the portion of the conductive material in the remaining portion of the conductive materials to the portion of the additional conductive contact.
11. The method of claim 10 , wherein forming the additional connection includes:
forming a first segment of the additional connection in the third opening;
forming a second segment of the additional connection in the fourth opening; and
forming a third segment of the additional connection to couple the first segment of the additional connection to the second segment of the additional connection.