Forming a cavity with a wet etch for backside contact formation

1. An integrated chip comprising:

a first source/drain region;

a second source/drain region spaced apart from the first source/drain region;

a channel structure extending between the first source/drain region and the second source/drain region;

a gate electrode arranged over the channel structure;

a first backside contact arranged below and coupled to the first source/drain region;

a backside dielectric extending laterally from a sidewall of the first backside contact and covering an entire lower surface of the second source/drain region; and

a first upper interconnect contact arranged over and coupled to the second source/drain region.

2. The integrated chip of claim 1 , further comprising:

a second upper interconnect contact arranged over and coupled to the gate electrode.

3. The integrated chip of claim 1 , wherein the channel structure comprises a plurality of nanosheet channel structures stacked over one another, the plurality of nanosheet channel structures extending in parallel with one another between the first source/drain region and the second source/drain region.

4. The integrated chip of claim 3 , wherein the gate electrode comprises a plurality of gate regions that are disposed above and below the plurality of nanosheet channel structures, respectively.

5. The integrated chip of claim 1 , wherein the first backside contact is arranged in a lower interconnect dielectric structure, and wherein the channel structure comprises a fin structure, wherein the fin structure continuously extends between the lower interconnect dielectric structure and the gate electrode.

6. The integrated chip of claim 1 , wherein the first backside contact has outermost sidewalls that are substantially planar.

7. The integrated chip of claim 1 , wherein the first backside contact has outermost sidewalls that are curved.

8. An integrated chip comprising:

a first source/drain region;

a second source/drain region spaced apart from the first source/drain region;

a channel structure extending between the first source/drain region and the second source/drain region;

a gate electrode arranged over the channel structure;

a first upper interconnect contact arranged over and coupled to the gate electrode; and

a backside contact arranged below and electrically coupled to the first source/drain region; and

wherein an upper surface of the first source/drain region and an upper surface of the second source/drain region nearest the first upper interconnect contact are co-planar with one another and are co-planar with an upper surface of the channel structure.

9. The integrated chip of claim 8 , wherein the first upper interconnect contact has a width that increases from a bottommost surface of the first upper interconnect contact to a topmost surface of the first upper interconnect contact.

10. The integrated chip of claim 8 , further comprising:

a second upper interconnect contact arranged over and coupled to the second source/drain region.

11. The integrated chip of claim 10 , wherein the second upper interconnect contact has a width that decreases from a topmost surface of the second upper interconnect contact to a bottommost surface of the second upper interconnect contact.

12. The integrated chip of claim 8 , wherein the channel structure comprises a plurality of nanosheet channel structures stacked over one another, the plurality of nanosheet channel structures extending in parallel with one another between the first source/drain region and the second source/drain region.

13. The integrated chip of claim 12 , wherein the gate electrode comprises a plurality of gate regions that are disposed above and below the plurality of nanosheet channel structures, respectively.

14. An integrated chip comprising:

a first source/drain region;

a second source/drain region spaced apart from the first source/drain region;

a channel structure extending between the first source/drain region and the second source/drain region;

a gate electrode arranged over the channel structure;

an upper interconnect contact having tapered sidewalls, the upper interconnect contact being arranged over and coupled to the first source/drain region and the upper interconnect contact being the only contact directly contacting the first source/drain region; and

a backside contact arranged below and coupled to the second source/drain region wherein the backside contact being the only contact directly contacting the second source/drain region.

15. The integrated chip of claim 14 , wherein the upper interconnect contact has a width that increases from a bottommost surface of the upper interconnect contact to a topmost surface of the upper interconnect contact.

16. The integrated chip of claim 14 , wherein the upper interconnect contact is coupled to the first source/drain region and further comprising:

an additional upper interconnect contact arranged over and coupled to the gate electrode.

17. The integrated chip of claim 16 , wherein the additional upper interconnect contact has a width that decreases from a topmost surface of the additional upper interconnect contact to a bottommost surface of the additional upper interconnect contact.

18. The integrated chip of claim 14 , wherein the channel structure comprises a plurality of nanosheet channel structures stacked over one another, the plurality of nanosheet channel structures extending in parallel with one another between the first source/drain region and the second source/drain region.

19. The integrated chip of claim 18 , wherein the gate electrode comprises a plurality of gate regions that are disposed above and below the plurality of nanosheet channel structures, respectively.

20. The integrated chip of claim 14 , further comprising:

a backside dielectric extending laterally from a sidewall of the backside contact and covering an entire lower surface of the first source/drain region.