Semiconductor memory device, memory system, and write method
According to one embodiment, a memory system includes a semiconductor memory device including a memory cell capable of holding at least 4-bit data and a controller configured to control a first write operation and a second write operation based on the 4-bit data. The controller includes a conversion circuit configured to convert 4-bit data into 2-bit data. The semiconductor memory device includes a recovery controller configured to recover the 4-bit data based on the converted 2-bit data and data written in the memory cell by the first write operation. The first write operation is executed based on the 4-bit data received from the controller, and the second write operation is executed based on the 4-bit data recovered by the recovery controller.
1. A memory system comprising:
a semiconductor memory device having a first memory region including a first memory cell capable of holding at least 4-bit data and a second memory region including a plurality of second memory cells capable of holding at least 1-bit data; and
a controller configured to control a first write operation and a second write operation based on the 4-bit data in the semiconductor memory device,
wherein the controller includes a conversion circuit which converts the 4-bit data into n-bit data, n being an integer,
the semiconductor memory device includes a recovery controller configured to recover the 4-bit data based on the converted n-bit data and data written in the first memory cell by the first write operation,
when the controller detects power shutdown, the conversion circuit converts the 4-bit data used for the first write operation into the n-bit data, and
the controller instructs the semiconductor memory device to write each of the n-bit data in different second memory cells of the plurality of second memory cells.
2. The system according to claim 1 , wherein
after power recovery, the controller instructs the semiconductor memory device to perform read operation of the n-bit data written in the second memory region, recovery operation of the 4-bit data, and the second write operation.
3. The system according to claim 1 , wherein
a threshold voltage of the first memory cell is included in any one of a plurality of threshold distributions corresponding to the 4-bit data, and
assignment of the n-bit data to the plurality of threshold distributions is different by 1 bit between the threshold distributions adjacent to each other.
4. A method for controlling a memory system,
the memory system including:
a semiconductor memory device having a first memory region including a first memory cell capable of holding at least 4-bit data and a second memory region including a plurality of second memory cells capable of holding at least 1-bit data; and
a controller configured to control a first write operation and a second write operation based on the 4-bit data in the semiconductor memory device,
wherein the controller includes a conversion circuit which converts the 4-bit data into n-bit data, n being an integer, and
the semiconductor memory device includes a recovery controller configured to recover the 4-bit data based on the converted n-bit data and data written in the first memory cell by the first write operation,
the method comprising:
upon detection of power shutdown, using the conversion circuit, converting the 4-bit data used for the first write operation into the n-bit data; and
using the controller, instructing the semiconductor memory device to write each of the n-bit data in different second memory cells of the plurality of second memory cells.
5. The method according to claim 4 , wherein
after power recovery, using the controller, instructing the semiconductor memory device to perform read operation of the n-bit data written in the second memory region, recovery operation of the 4-bit data, and the second write operation.
6. The method according to claim 4 , wherein
a threshold voltage of the first memory cell is included in any one of a plurality of threshold distributions corresponding to the 4-bit data, and
assignment of the n-bit data to the plurality of threshold distributions is different by 1 bit between the threshold distributions adjacent to each other.
7. A semiconductor memory device comprising:
a memory cell array including a first memory cell capable of holding at least n-bit data, n being an integer of 4 or more; and
a conversion circuit configured to recover the n-bit data based on m-bit data generated by converting the n-bit data and data written in the first memory cell, m being an integer smaller than n,
wherein an operation of writing the n-bit data in the first memory cell includes a first write operation and a second write operation,
the first write operation is executed based on the n-bit data received from the outside, and
the second write operation is executed based on the n-bit data recovered by the conversion circuit.
8. The device according to claim 7 , wherein
after the first write operation, the conversion circuit converts the n-bit data into the n-bit data, the converted n-bit data is outputted to the outside, and
before the second write operation, the conversion circuit recovers the n-bit data based on the n-bit data received from the outside and the data read from the first memory cell.
9. The device according to claim 7 , wherein
the memory cell array further includes a plurality of second memory cells capable of holding at least 1-bit data,
each of the n-bit data are written in different second memory cells of the plurality of second memory cells, and
before the second write operation, the conversion circuit recovers the n-bit data based on the n-bit data read from the second memory cells and the data read from the first memory cell.
10. The device according to claim 7 , wherein
the conversion circuit recovers the n-bit data based on the m-bit data generated and (n-m)-bit data received from the outside.
11. The device according to claim 10 , further comprising:
a semiconductor substrate.
12. The device according to claim 10 , wherein
n is 4, and
m is 2.
13. The device according to claim 12 , wherein
the first memory cell is provided in plurality, and
the first memory cells are configured to have one of 16 threshold voltage distributions corresponding to the 4-bit data.
14. The device according to claim 13 , wherein
the 2-bit data corresponds to 16 threshold voltage distributions different from the 16 threshold voltage distributions of the 4-bit data.
15. The device according to claim 14 , wherein
the 16 threshold voltage distributions of the 2-bit data correspond to the 16 threshold voltage distributions of the 4-bit data, respectively.
16. The device according to claim 15 , wherein
each of the 16 threshold voltage distributions of the 4-bit data is thinner a corresponding one of the 16 threshold voltage distributions of the 4-bit data, respectively.
17. The device according to claim 13 , further comprising:
a word line connected to the first memory cells; and
a plurality of bit lines connected to the first memory cells, respectively.
18. The device according to claim 17 , further comprising:
a plurality of sense amplifiers connected to the bit lines, respectively.