Passive RFID tag with embedded sensor interface
A CMOS analog sensor interface circuit embedded in a passive RFID platform can provide accurate data conversion from analog signals to their digital representations. This interface can also utilize the RFID platform to achieve wireless data transmission. The disclosed sensor interface circuit includes signal filtering, signal amplification, as well as signal digitization. These circuits are all designed under the constraints of low-power operation on a noisy silicon substrate. By using the disclosed circuit design, fully passive wireless sensing network that can integrate with heterogeneous sensors (resistance, voltage, current types) can be designed. The advantages of low-cost, small feature size, and the ability to interface with analog sensors can enable large-scale deployment of such kind of RFIDs, both for consumer electronics like in-door monitoring and industrial sensing applications like the grid, electric vehicle, motor, and other critical infrastructures.
1. A passive Radio Frequency Identification (RFID) tag comprising:
an RFID chip; and
a sensor interface integrated with the RFID chip in the passive RFID tag, the sensor interface including an instrumentation amplifier including:
a first capacitor array connected to a positive terminal of an input voltage and a negative terminal of a reference voltage, the first capacitor array including a first input capacitor bank having a plurality of capacitors, a first feedback capacitor, and a first reference capacitor bank having a plurality of capacitors,
wherein the plurality of capacitors of the first input capacitor bank include a first capacitor, a second capacitor, and a third capacitor,
a second capacitor array connected to a negative terminal of the input voltage and a positive terminal of the reference voltage, the second capacitor array including a second input capacitor bank having a plurality of capacitors, a second feedback capacitor, and a second reference capacitor bank having a plurality of capacitors
wherein the input voltage is amplified by a gain determined by a ratio of a total capacitance (C IN_TOTAL ) divided by a feedback capacitance (C FB ) of the first feedback capacitor,
wherein the total capacitance (C IN_TOTAL ) is equal to a sum of a first capacitance of the first capacitor and a second capacitance of the second capacitor if a set gain is high,
wherein the total capacitance (C IN_TOTAL ) is equal to a sum of the first capacitance of the first capacitor and a third capacitance of the third capacitor if the set gain is low,
wherein an effective input voltage (V net ) to the instrumentation amplifier is determined by:
V
n
e
t
=
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V
i
n
+
-
V
i
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-
)
-
C
R
T
O
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A
L
C
IN
T
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T
A
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(
V
ref
+
-
V
ref
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)
wherein
V in+ is a voltage of the positive terminal of the input voltage,
V in− is a voltage of the negative terminal of the input voltage,
C R TOTAL is a total capacitance of the first reference capacitor bank,
V ref+ is a voltage of the positive terminal of the reference voltage, and
V ref− is a voltage of the negative terminal of the reference voltage.
2. The passive RFID tag of claim 1 , wherein the instrumentation amplifier further includes a two-stage error amplifier configured to utilize Miller compensation.
3. The passive RFID tag of claim 1 , wherein the instrumentation amplifier includes a capacitively-coupled instrumentation amplifier core.
4. The passive RFID tag of claim 1 , configured such that the instrumentation amplifier is only enabled if signal amplification is performed via the passive RFID tag.
5. The passive RFID tag of claim 1 , configured such that the instrumentation amplifier is disabled during direct voltage signal conversion.
6. The passive RFID tag of claim 1 , configured such that the instrumentation amplifier is disabled during temperature sensing via the sensor interface.
7. The passive RFID tag of claim 1 , wherein the instrumentation amplifier further includes two diode-connected PMOS configured to maintain a common level voltage at a first node connected to the first capacitor array and at a second node connected to the second capacitor array.
8. The passive RFID tag of claim 7 , wherein the instrumentation amplifier is configured such that a first resistor is in series with the first node with a first transmission gate therebetween and a second resistor is in series with the second node with a second transmission gate therebetween, and
wherein during startup of the instrumentation amplifier, a resistance at the first node is equal to a first resistance of the first resistor and a resistance at the second node is equal to a second resistance of the second resistor.