IP Library › Granted Patent US 12,362,304
Granted Patent B2
US 12,362,304 · App. 17/876,151 · Granted Jul 15, 2025

Bonding layer and process of making

Inventor: Robert D. Clark (Albany, NY)
Assignee: Tokyo Electron Limited
H01L24/08H01L24/03H01L24/05H01L24/80H01L25/0657H01L2224/0341H01L2224/03444H01L2224/05541H01L2224/05578H01L2224/05624H01L2224/05687H01L2224/0801H01L2224/08145H01L2224/08501H01L2224/80203H01L2224/80232H01L2224/80895H01L2224/80896H01L2224/80948H01L2225/06524H01L2225/06527
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Quick Facts
Patent No.
US 12,362,304
App. No.
17/876,151
Granted
Jul 15, 2025
Kind
B2
Abstract

A process for forming a semiconductor package is disclosed. The process includes providing a first substrate including a first dielectric layer. The process includes overlaying a first surface of the first dielectric layer with a first bonding layer that includes aluminum. The process includes providing a second substrate including a second dielectric layer. The process includes overlaying a second surface of the second dielectric layer with a second bonding layer that includes alkoxy-siloxide. The process includes forming a third bonding layer by combining the first bonding layer and the second bonding layer so as to bond the first substrate to the second substrate.

Claims (27)

1. A process, comprising:

providing a first substrate including a first dielectric layer;

overlaying a first surface of the first dielectric layer with a first bonding layer that includes aluminum;

providing a second substrate including a second dielectric layer;

overlaying a second surface of the second dielectric layer with a second bonding layer that includes alkoxy-siloxide; and

forming a third bonding layer by combining the first bonding layer and the second bonding layer so as to bond the first substrate to the second substrate.

2. The process of claim 1 , further comprising applying a vapor or liquid phase of trimethyl aluminum over the second surface to form the second bonding layer.

3. The process of claim 1 , further comprising applying a vapor or liquid phase of dimethyl aluminum iso-propoxide over the second surface to form the second bonding layer.

4. The process of claim 1 , further comprising applying a vapor or liquid phase of tris(tert-pentoxy)silicon(dimethylamide) over the second surface to form the second bonding layer.

5. The process of claim 1 , further comprising:

physically contacting the first bonding layer with the second bonding layer; and

annealing at least the contacted first and second bonding layers at an elevated temperature to form the third bonding layer.

6. The process of claim 5 , wherein the elevated temperature is less than about 500 Celsius degrees.

7. The process of claim 5 , wherein annealing at least the contacted first and second bonding layers causes the aluminum of the first bonding layer to catalyze rearrangement of alkoxide ligands of the second bonding layer via a beta-elimination process.

8. The process of claim 1 , wherein each of the first bonding layer and the second bonding layer has a thickness thinner than about 2 nanometers (nm).

9. The process of claim 1 , wherein the first dielectric layer embeds a first interconnect structure with its first upper surface not overlaid by the first dielectric layer or the first bonding layer, and the second dielectric layer embeds a second interconnect structure with its second upper surface not overlaid by the second dielectric layer or the second bonding layer.

10. The process of claim 9 , concurrently with forming the third bonding layer, further comprising physically contacting the first upper surface of the first interconnect structure with the second upper surface of the second interconnect structure.

11. A process, comprising:

forming a first dielectric layer over a first substrate, wherein the first dielectric layer embeds a first interconnect structure;

overlaying a first surface of the first dielectric layer with a first bonding layer that includes aluminum;

forming a second dielectric layer over a second substrate, wherein the second dielectric layer embeds a second interconnect structure;

overlaying a second surface of the second dielectric layer with a second bonding layer that includes alkoxy-siloxide; and

connecting the first interconnect structure to the second interconnect structure based on combining the first bonding layer and the second bonding layer.

12. The process of claim 11 , wherein combing the first bonding layer and the second bonding layer further comprises:

physically contacting the first bonding layer with the second bonding layer; and

annealing at least the contacted first and second bonding layers at an elevated temperature to form a third bonding layer that comprises AlSiO.

13. The process of claim 12 , wherein the elevated temperature is less than about 500 Celsius degrees.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 28, 2022
From: CLARK, ROBERT D.
To: TOKYO ELECTRON LIMITED
Reel/Frame 060660/0592 →
Continuity (2)
Provisional Application 63240312 · Sep 2, 2021
Related Publication 20230062465A1 · Mar 2, 2023
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