Wafer-to-wafer bonding structure

1. A wafer-to-wafer bonding structure comprising:

a first wafer including a first conductive pad in a first insulating layer and a first barrier layer surrounding a lower surface and side surfaces of the first conductive pad;

a second wafer including a second conductive pad in a second insulating layer and a second barrier layer surrounding a lower surface and side surfaces of the second conductive pad, the second insulating layer being bonded to the first insulating layer, and at least a portion of an upper surface of the second conductive pad being partially or entirely bonded to at least a portion of an upper surface of the first conductive pad; and

a third barrier layer only between portions of the first and second wafers where the first and second conductive pads are not bonded to each other,

wherein the first conductive pad is a first recessed conductive pad and a first seed layer is on the first recessed conductive pad, and

wherein the second conductive pad is a second recessed conductive pad and a second seed layer is on the second recessed conductive pad.

2. The wafer-to-wafer bonding structure of claim 1 , wherein

the second conductive pad has the same width as the first conductive pad,

the third barrier layer is between portions of the second insulating layer and the first conductive pad that are not bonded to the second conductive pad, and

the third barrier layer is between portions of the first insulating layer and the second conductive pad that are not bonded to the first conductive pad.

3. The wafer-to-wafer bonding structure of claim 1 , wherein

a width of the second conductive pad is less than that of the first conductive pad, and

the third barrier layer is between the second insulating layer and the first conductive pad that is not bonded to the second conductive pad.

4. The wafer-to-wafer bonding structure of claim 1 , wherein the third barrier layer is around a portion of the first conductive pad and around a portion of the second conductive pad.

5. The wafer-to-wafer bonding structure of claim 1 , wherein the third barrier layer is a self-forming barrier layer.

6. The wafer-to-wafer bonding structure of claim 1 , wherein

the first and second conductive pads include copper (Cu), and

the first and second insulating layers include silicon oxide.

7. The wafer-to-wafer bonding structure of claim 6 , wherein

the third barrier layer includes silicon and a metal more prone to oxidize than Cu.

8. The wafer-to-wafer bonding structure of claim 1 , wherein an upper surface of the first insulating layer and an upper surface of the second insulating layer are plasma-activated surfaces.

9. The wafer-to-wafer bonding structure of claim 1 , wherein

the first conductive pad includes a first lower conductive pad and a first upper conductive pad, and the first barrier layer surrounds lower surfaces and side surfaces of the first lower conductive pad and the first upper conductive pad, and

the second conductive pad includes a second lower conductive pad and a second upper conductive pad, and the second barrier layer surrounds lower surfaces and side surfaces of the second lower conductive pad and the second upper conductive pad.

10. The wafer-to-wafer bonding structure of claim 1 , wherein

the first conductive pad includes a first lower conductive pad and a first upper conductive pad, the first barrier layer includes a first lower barrier layer and a first upper barrier layer, the first lower barrier layer surrounding lower surfaces and side surfaces of the first lower conductive pad and the first upper barrier layer surrounding lower surfaces and side surfaces of the first upper conductive pad, and

the second conductive pad includes a second lower conductive pad and a second upper conductive pad, the second barrier layer includes a second lower barrier layer and a second upper barrier layer, the second lower barrier layer surrounding lower surfaces and side surfaces of the second lower conductive pad and the second upper barrier layer surrounding lower surfaces and side surfaces of the second upper conductive pad.

11. The wafer-to-wafer bonding structure of claim 1 , wherein

the first conductive pad includes a first lower conductive pad and a first upper conductive pad, the first upper conductive pad having a width greater than a width of the first lower conductive pad, and

the second conductive pad includes a second lower conductive pad and a second upper conductive pad, the second upper conductive pad having a width greater than a width of the second lower conductive pad.

12. The wafer-to-wafer bonding structure of claim 1 , wherein

the first wafer further comprises a first multi-layered wiring layer, the first insulating layer is on the first multi-layered wiring layer, and the first conductive pad is electrically connected to the first multi-layered wiring layer through a first vertical contact in the first insulating layer, and

the second wafer further comprises a second multi-layered wiring layer, the second insulating layer is on the second multi-layered wiring layer, and the second conductive pad is electrically connected to the second multi-layered wiring layer through a second vertical contact in the second insulating layer.

13. A wafer-to-wafer bonding structure comprising:

a first wafer including,

a first semiconductor layer,

a first multi-layered wiring layer on the first semiconductor layer,

a first insulating layer on the first multi-layered wiring layer,

a first conductive pad penetrating the first insulating layer, and

a first barrier layer surrounding the first conductive pad; and

a second wafer including,

a second insulating layer on the first insulating layer, the second insulating layer bonded to the first insulating layer,

a second conductive pad penetrating the second insulating layer and bonded to a portion of the first conductive pad,

a second barrier layer surrounding the second conductive pad,

a second multi-layered wiring layer on the second insulating layer and the second conductive pad, and

a second semiconductor layer on the second multi-layered wiring layer; and

a third barrier layer only between the first and second wafers where the first and second conductive pads not bonded to each other,

wherein the first conductive pad is a first recessed conductive pad and a first seed layer is on the first recessed conductive pad, and

wherein the second conductive pad is a second recessed conductive pad and a second seed layer is on the second recessed conductive pad.

14. The wafer-to-wafer bonding structure of claim 13 , wherein

the first barrier layer is on a lower surface of the first conductive pad, and the first conductive pad is electrically connected to the first multi-layered wiring layer through the first barrier layer, and

the second barrier layer is on an upper surface of the second conductive pad, and the second conductive pad is electrically connected to the second multi-layered wiring layer through the second barrier layer.

15. The wafer-to-wafer bonding structure of claim 13 , wherein

the third barrier layer is between the second insulating layer and the first conductive pad that is not bonded to the second conductive pad, and between the first insulating layer and the second conductive pad that is not bonded to the first conductive pad, or

the third barrier layer is between the second insulating layer and the first conductive pad that is not bonded to the second conductive pad.

16. A bonding structure comprising:

a first wafer including a first insulating layer and a first conductive pad embedded in the first insulating layer;

a second wafer bonded to the first wafer, the second wafer including a second insulating layer and a second conductive pad embedded in the second insulating layer, the second conductive pad overlapping a portion of the first conductive pad such that the first and second conductive pads are not vertically aligned; and

a barrier metal layer only on an interface between the first and second wafers where the first and second conductive pads do not overlap,

wherein the first conductive pad is a first recessed conductive pad and a first seed layer is on the first recessed conductive pad, and

wherein the second conductive pad is a second recessed conductive pad and a second seed layer is on the second recessed conductive pad.

17. The bonding structure of claim 16 , wherein

the second conductive pad has the same width as the first conductive pad,

the barrier metal layer is between the second insulating layer and the portion of the first conductive pad that is not overlapped by the second conductive pad, and

the barrier metal layer is between the first insulating layer and the portion of the second conductive pad not overlapping the first conductive pad.

18. The bonding structure of claim 16 , wherein

a width of the second conductive pad is less than that of the first conductive pad, and

the barrier metal layer is between the second insulating layer and the portion of the first conductive pad that is not overlapped by the second conductive pad.

19. The bonding structure of claim 16 , wherein

the first and second conductive pads include copper (Cu),

the barrier metal layer includes MnSiO or AlSiO, and

the first and second insulating layers include silicon oxide.

20. The bonding structure of claim 16 , wherein

the first wafer further comprises a first metal layer surrounding a lower surface and side surfaces of the first conductive pad,

the second wafer further comprises a second metal layer surrounding a lower surface and side surfaces of the second conductive pad, and

each of the first and second metal layers include titanium (Ti), tantalum (Ta), titanium nitride (TiN), or tantalum nitride (TaN).