IP Library Granted Patent US 12,685,236
Granted Patent B2
US 12,685,236 · App. 17/878,647 · Granted Jul 14, 2026

Semiconductor device packages and methods of forming the same

Inventors: Chi-Yang Yu (Zhongli City, TW); Chin-Liang Chen (Kaohsiung City, TW); Hao-Cheng Hou (Hsinchu, TW); Jung Wei Cheng (Hsinchu, TW); Yu-Min Liang (Zhongli City, TW); Tsung-Ding Wang (Tainan, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H10W90/701H10W70/05H10W70/093H10W70/65H10W70/685H10W70/69H10W70/695H10W90/00H10W90/401H10W70/095H10W74/00H10W74/15H10W90/724H10W90/734
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Quick Facts
Patent No.
US 12,685,236
App. No.
17/878,647
Granted
Jul 14, 2026
Kind
B2
Abstract

Semiconductor device packages and methods of forming the same are discussed. In an embodiment, a device includes: a redistribution structure comprising an upper dielectric layer and an under-bump metallization; a buffer feature on the under-bump metallization and the upper dielectric layer, the buffer feature covering an edge of the under-bump metallization, the buffer feature bonded to the upper dielectric layer; a reflowable connector extending through the buffer feature, the reflowable connector coupled to the under-bump metallization; an interposer coupled to the reflowable connector; and an encapsulant around the interposer and the reflowable connector, the encapsulant different from the buffer feature.

Claims (45)

1 . A method comprising:

forming a redistribution structure on a carrier substrate;

forming dangling bonds on an upper dielectric layer of the redistribution structure by treating the upper dielectric layer;

forming a buffer layer on the upper dielectric layer and on an under-bump metallization of the redistribution structure by bonding a buffer material to the dangling bonds;

patterning the buffer layer with a first opening exposing the under-bump metallization;

connecting an interposer to the under-bump metallization with a first conductive connector, the first conductive connector disposed in the first opening;

encapsulating the interposer and the first conductive connector;

after encapsulating the interposer and the first conductive connector, exposing a lower dielectric layer of the redistribution structure by removing the carrier substrate;

patterning the lower dielectric layer with a second opening exposing a metallization pattern of the redistribution structure; and

connecting a semiconductor device to the metallization pattern with a second conductive connector, the second conductive connector disposed in the second opening.

2 . The method of claim 1 , wherein the dangling bonds are hydroxyl groups and treating the upper dielectric layer comprises performing a plasma treatment process with O 2 , N 2 , H 2 , or a combination thereof.

3 . The method of claim 1 , wherein the buffer material is a photosensitive polymer and patterning the buffer layer comprises exposing the buffer layer to light and developing the buffer layer.

4 . The method of claim 1 , wherein the buffer material is a molding compound and patterning the buffer layer comprises drilling the buffer layer.

5 . The method of claim 1 , wherein the upper dielectric layer has a first thickness, the buffer layer has a second thickness, and the second thickness is greater than the first thickness.

6 . The method of claim 1 , wherein the upper dielectric layer is disposed on a middle dielectric layer of the redistribution structure, a first bonding strength between the upper dielectric layer and the middle dielectric layer being less than a second bonding strength between the upper dielectric layer and the buffer layer.

7 . The method of claim 1 , wherein the buffer layer completely covers the upper dielectric layer after the patterning the buffer layer.

8 . The method of claim 1 , wherein patterning the buffer layer exposes a portion of the upper dielectric layer.

9 . A method comprising:

forming a redistribution structure on a carrier substrate;

forming a buffer layer on an upper dielectric layer and under-bump metallizations of the redistribution structure;

patterning the buffer layer to expose the under-bump metallizations;

connecting an interposer to the under-bump metallizations, the interposer having a first coefficient of thermal expansion;

removing the carrier substrate to expose a lower dielectric layer of the redistribution structure;

patterning the lower dielectric layer to expose a metallization pattern of the redistribution structure; and

connecting a semiconductor device to the metallization pattern, the semiconductor device having a second coefficient of thermal expansion, the second coefficient of thermal expansion less than the first coefficient of thermal expansion.

10 . The method of claim 9 , wherein the interposer comprises an organic substrate.

11 . The method of claim 9 , wherein the upper dielectric layer comprises a photosensitive polymer and the lower dielectric layer comprises a photoinsensitive polymer.

12 . The method of claim 9 , wherein the buffer layer comprises the same material as the upper dielectric layer.

13 . The method of claim 9 , wherein the buffer layer comprises a different material from the upper dielectric layer.

14 . A method comprising:

forming a redistribution structure on a carrier substrate, the redistribution structure including an outer insulating layer;

forming an under-bump metallization on a first side of the redistribution structure, the under-bump metallization extending through the outer insulating layer;

forming a buffer layer over the first side of the redistribution structure and the under-bump metallization, wherein the outer insulating layer is disposed on a middle dielectric layer of the redistribution structure, a first bonding strength between the outer insulating layer and the middle dielectric layer being less than a second bonding strength between the outer insulating layer and the buffer layer;

curing the buffer layer, wherein the buffer layer bonds to the outer insulating layer using covalent bonds;

patterning the buffer layer to expose a surface of the under-bump metallization, the buffer layer remaining along sidewalls of the under-bump metallization;

attaching an interposer to the under-bump metallization using a first conductive connector, the interposer having a first coefficient of thermal expansion (CTE); and

attaching a semiconductor device to a second side of the redistribution structure, the semiconductor device having a second CTE different than the first CTE.

15 . The method of claim 14 , wherein the buffer layer has a Young's modulus in a range of 0.05 GPa to 30 GPa.

16 . The method of claim 14 , wherein patterning the buffer layer comprises patterning a ring around the under-bump metallization.

17 . The method of claim 14 , wherein the redistribution structure includes an outer insulating layer, wherein the under-bump metallization extends through the outer insulating layer, wherein the buffer layer completely covers the outer insulating layer after patterning the buffer layer.

18 . The method of claim 14 , wherein the buffer layer comprises a resin with fillers disposed therein.

19 . The method of claim 14 , further comprising:

prior to forming the buffer layer, performing a treatment process on the outer insulating layer to create dangling bonds.

20 . The method of claim 1 , further comprising:

curing the buffer layer, wherein after curing the buffer layer is bonded to the upper dielectric layer with covalent bonds.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2022
From: YU, CHI-YANG; CHEN, CHIN-LIANG; HOU, HAO-CHENG; CHENG, JUNG WEI; LIANG, YU-MIN; WANG, TSUNG-DING
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 060689/0162 →
Continuity (1)
Related Publication 20240038646A1 · Feb 1, 2024
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