Granted Patent B2

US 12,453,159 · App. 17/883,677 · Granted Oct 21, 2025

Inventors: Huan-Chieh Su (Tianzhong Township, TW); Cheng-Chi Chuang (New Taipei, TW); Chih-Hao Wang (Baoshan Township, TW); Kuo-Cheng Chiang (Zhubei, TW)

Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.

H10D64/254H10D30/014H10D30/43H10D30/6735H10D30/6757H10D62/121H10D64/017H10D64/251H10D84/0149H10D84/0158H10D84/038

Abstract

Claims (55)

1. A method for forming a semiconductor transistor device, comprising:

forming a stack of semiconductor layers as a channel structure;

forming a gate structure wrapping around the channel structure;

forming a first source/drain epitaxial structure and a second source/drain epitaxial structure on opposite ends of the channel structure;

etching a bottom of the second source/drain epitaxial structure to form a concave bottom surface;

forming a first dielectric liner overlying the second source/drain epitaxial structure; and

forming a source/drain contact along a sidewall of the first dielectric liner and contacting a bottom of the second source/drain epitaxial structure.

2. The method of claim 1 , further comprising:

etching a bottom of the first source/drain epitaxial structure to form a concave bottom surface prior to forming the source/drain contact; and

wherein the source/drain contact directly contacts the first source/drain epitaxial structure.

3. The method of claim 1 , wherein the first dielectric liner directly contacts a sidewall of the source/drain contact.

4. The method of claim 3 , wherein the source/drain contact is formed by:

etching a bottom of the first source/drain epitaxial structure to form a recess extended under the gate structure;

forming a dielectric cap within the recess; and

forming an opening through the dielectric cap and filling the opening with the first dielectric liner and the source/drain contact reaching on the first source/drain epitaxial structure.

5. The method of claim 4 , further comprising:

forming a second dielectric liner along sidewall and bottom surfaces of the recess prior to forming the dielectric cap; and

wherein the second dielectric liner is in direct contact with the concave bottom surface of the second source/drain epitaxial structure and a bottom surface of the gate structure.

6. The method of claim 4 , further comprising forming a middle isolation structure surrounding the gate structure, the first source/drain epitaxial structure, and the second source/drain epitaxial structure.

7. The method of claim 6 , further comprising forming a lower isolation structure under the middle isolation structure and surrounding the dielectric cap.

8. The method of claim 1 , wherein the channel structure is formed by a stack of semiconductor nanowires.

9. The method of claim 1 , further comprising:

forming a front-side interconnect structure over the gate structure and electrically connected to the gate structure through a gate contact; and

forming an interconnect structure under the first source/drain epitaxial structure and electrically connected to the first source/drain epitaxial structure through the source/drain contact.

10. The method of claim 1 , further comprising forming an inner spacer separating the gate structure from the first source/drain epitaxial structure and the second source/drain epitaxial structure.

11. A method for forming a semiconductor transistor device, comprising:

forming a stack of semiconductor layers as a channel structure;

forming a gate structure wrapping around the channel structure;

forming a first source/drain epitaxial structure and a second source/drain epitaxial structure on opposite ends of the channel structure;

forming a gate contact on the gate structure;

forming a source/drain contact under and contacting the first source/drain epitaxial structure;

forming a first dielectric liner along and contacting a sidewall of the second source/drain epitaxial structure and the gate structure; and

forming a dielectric cap under and extended along the second source/drain epitaxial structure and the gate structure.

12. The method of claim 11 , wherein a bottom surface of the second source/drain epitaxial structure has a concave shape along a first direction from the first source/drain epitaxial structure to the second source/drain epitaxial structure and along a second direction perpendicular to the first direction.

13. The method of claim 11 , wherein the second source/drain epitaxial structure has a bottom surface locating higher than a bottom surface of the gate structure.

14. The method of claim 11 , wherein the source/drain contact has a top surface locating higher than a bottom surface of the gate structure.

15. The method of claim 11 , further comprising:

forming a second dielectric liner between the source/drain contact and the first dielectric liner.

16. The method of claim 11 , wherein forming the gate structure comprises:

forming a gate electrode; and

forming a gate dielectric between the gate electrode and the channel structure.

17. The method of claim 11 , wherein forming the channel structure comprises forming a stack of semiconductor nanowires.

18. The method of claim 11 , further comprising forming an inner spacer separating with the gate structure from the first source/drain epitaxial structure and the second source/drain epitaxial structure.

19. The method of claim 11 , wherein the dielectric cap is formed by SiO 2 , SiN, SiCN, SiOCN, Al 2 O 3 , AlON, ZrO 2 , HfO 2 , or combinations thereof.

20. A method of forming a semiconductor transistor device, the method comprising:

forming a fin structure over a substrate by alternately stacking first semiconductor layers and second semiconductor layers;

forming a dummy gate structure over the fin structure;

removing a portion of the fin structure uncovered by the dummy gate structure;

forming inner spacers on opposite sides of remaining portions of the first semiconductor layers;

forming a first source/drain epitaxial structure and a second source/drain epitaxial structure on opposite ends of the fin structure;

replacing the dummy gate structure and the first semiconductor layers with a metal gate structure;

removing the substrate and forming a capping trench to expose a bottom surface of the metal gate structure and a bottom surface of the second source/drain epitaxial structure;

performing an isotropic etch to recess the bottom surface of the second source/drain epitaxial structure to have a concave shape;

forming a dielectric cap in the capping trench; and

forming a source/drain contact under and contacting the first source/drain epitaxial structure.

Assignments (1)

Continuity (3)

References Cited (31)