IP Library Granted Patent US 12,652,837
Granted Patent B2
US 12,652,837 · App. 17/886,797 · Granted Jun 9, 2026

Semiconductor device and methods of fabrication thereof

Inventors: Cheng-Wei Chang (Taipei, TW); Shahaji B. More (Hsinchu, TW); Shuen-Shin Liang (Hsinchu, TW); Sung-Li Wang (Hsinchu, TW); Yi-Ying Liu (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H10D62/151H10D30/014H10D30/031H10D30/43H10D30/6735H10D30/6757H10D62/121H10D64/0112H10D64/017H10D64/62
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,652,837
App. No.
17/886,797
Granted
Jun 9, 2026
Kind
B2
Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a source/drain epitaxial feature disposed over a substrate, wherein the source/drain epitaxial feature comprises a first epitaxial layer, a second epitaxial layer in contact with the first epitaxial layer, wherein the second epitaxial layer has a first dopant concentration, and a third epitaxial layer having sidewalls enclosed by the second epitaxial layer, wherein the third epitaxial layer has a second dopant concentration higher than the first dopant concentration. The semiconductor device structure also includes a source/drain cap layer disposed above and in contact with the second epitaxial layer and the third epitaxial layer, wherein the source/drain cap layer has a third dopant concentration higher than the second dopant concentration, and a silicide layer disposed above and in contact with the source/drain cap layer.

Claims (39)

1 . A semiconductor device structure, comprising:

a source/drain epitaxial feature disposed over a substrate, wherein the source/drain epitaxial feature comprises:

a first epitaxial layer; a second epitaxial layer in contact with the first epitaxial layer, the second epitaxial layer having a first dopant concentration; and a third epitaxial layer having sidewalls enclosed by the second epitaxial layer, the third epitaxial layer having a second dopant concentration higher than the first dopant concentration; a source/drain cap layer disposed above and in contact with the second epitaxial layer and the third epitaxial layer, wherein the source/drain cap layer having has a third dopant concentration higher than the second dopant concentration, and the source/drain cap layer has a first thickness and a silicide layer has a second thickness greater than the first thickness; and the silicide layer disposed above and in contact with the source/drain cap layer.

2 . The semiconductor device structure of claim 1 , wherein the source/drain epitaxial feature is located at a p-type device region of the substrate, and the source/drain cap layer is a boron-doped silicon.

3 . The semiconductor device structure of claim 2 , wherein the source/drain cap layer has an atomic percentage of boron in a range of about 4 at. % to about 15 at. %.

4 . The semiconductor device structure of claim 3 , wherein the third epitaxial layer is a boron-doped silicon germanium having a first boron concentration, and the source/drain cap layer has a second boron concentration that is about 10% to about 30% higher than the first boron concentration.

5 . The semiconductor device structure of claim 4 , wherein the source/drain cap layer further comprises germanium dopants.

6 . The semiconductor device structure of claim 5 , wherein the source/drain cap layer has a first germanium concentration, and the third epitaxial layer has a second germanium concentration higher than the first germanium concentration.

7 . The semiconductor device structure of claim 6 , wherein the silicide layer comprises germanium dopants, and the silicide layer has a third germanium concentration lower than the first germanium concentration.

8 . The semiconductor device structure of claim 1 , wherein the second epitaxial layer has a zig-zag shaped or a saw-tooth shaped profile.

9 . The semiconductor device structure of claim 1 , wherein a bottom of the second epitaxial layer contacting the first epitaxial layer has a first width, and a bottom of the source/drain cap layer contacting the third epitaxial layer has a second width less than the first width.

10 . A semiconductor device structure, comprising:

two or more semiconductor layers stacked vertically over a substrate;

a gate electrode layer surrounding a portion of one of the two or more semiconductor layers;

a source/drain epitaxial feature disposed over the substrate and adjacent the two or more semiconductor layers, the source/drain epitaxial feature comprising:

a first epitaxial layer disposed over the substrate; and

a second epitaxial layer having at least three surfaces in contact with the first epitaxial layer, the second epitaxial layer having a first dopant concentration; and

a source/drain cap layer disposed above and in contact with the first epitaxial layer and the second epitaxial layer, the source/drain cap layer having a second dopant concentration greater than the first dopant concentration, a portion of the source/drain cap layer contacting a first side of the second epitaxial layer defines a first interface, and a portion of the source/drain cap layer contacting a second side of the second epitaxial layer defines a second interface,

wherein the first interface extends along a first direction, the second interface extends along a second direction, and the first direction forms an angle less than about 90 degrees with respect to the second direction;

a silicide layer disposed above and in contact with the source/drain cap layer, wherein a portion of the source/drain cap layer between the second epitaxial layer and the silicide layer has a first thickness, and a portion of the source/drain cap layer between the first epitaxial layer and the silicide layer has a second thickness less than the first thickness.

11 . The semiconductor device structure of claim 10 , wherein the angle is in a range of about 40 degrees to about 80 degrees.

12 . The semiconductor device structure of claim 10 , further comprising:

a facetted structure disposed between and in contact with the source/drain cap layer and a topmost semiconductor layer of the two or more semiconductor layers.

13 . The semiconductor device structure of claim 10 , wherein the source/drain cap layer is a boron-rich silicon, and the third epitaxial layer is a boron-doped silicon germanium.

14 . The semiconductor device structure of claim 13 , wherein the source/drain cap layer has a boron concentration that is about 10% to about 30% higher than a boron concentration of the third epitaxial layer.

15 . A semiconductor device structure, comprising:

two or more semiconductor layers stacked vertically over a substrate;

a gate electrode layer surrounding a portion of one of the two or more semiconductor layers;

a source/drain epitaxial feature disposed over the substrate and adjacent the two or more semiconductor layers, the source/drain epitaxial feature comprising:

a first epitaxial layer disposed over the substrate; and

a second epitaxial layer having at least three surfaces in contact with the first epitaxial layer, the second epitaxial layer having a first dopant concentration; and

a facetted structure disposed on two or more semiconductor layers; and

a source/drain cap layer having a substantially concave profile and in contact with the first epitaxial layer, the second epitaxial layer, and the facetted structure, wherein the source/drain cap layer has a second dopant concentration greater than the first dopant concentration;

a silicide layer disposed above and in contact with the source/drain cap layer, wherein a portion of the source/drain cap layer between the second epitaxial layer and the silicide layer has a first thickness, and a portion of the source/drain cap layer between the first epitaxial layer and the silicide layer has a second thickness less than the first thickness.

16 . The semiconductor device structure of claim 1 , wherein the third dopant concentration is in a range of about 4 at. % to about 15 at. %.

17 . The semiconductor device structure of claim 1 , wherein the source/drain cap layer comprises boron-doped silicon and the third epitaxial layer comprises boron-doped silicon germanium.

18 . The semiconductor device structure of claim 10 , wherein the second dopant concentration is about 10% to about 30% higher than the first dopant concentration.

19 . The semiconductor device structure of claim 15 , wherein the second dopant concentration is in a range of about 4 at. % to about 15 at. %.

20 . The semiconductor device structure of claim 15 , wherein the source/drain cap layer is a boron-rich silicon layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 25, 2022
From: CHANG, CHENG-WEI; MORE, SHAHAJI B.; LIANG, SHUEN-SHIN; WANG, SUNG-LI; LIU, YI-YING
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 060902/0339 →
Continuity (1)
Related Publication 20240055485A1 · Feb 15, 2024
References Cited (16)
US 9209247B2 · Colinge et al. · 2015 [cited by applicant]
US 9236267B2 · De et al. · 2016 [cited by applicant]
US 9412817B2 · Yang et al. · 2016 [cited by applicant]
US 9412828B2 · Ching et al. · 2016 [cited by applicant]
US 9472618B2 · Oxland · 2016 [cited by applicant]
US 9502265B1 · Jiang et al. · 2016 [cited by applicant]
US 9520482B1 · Chang et al. · 2016 [cited by applicant]
US 9536738B2 · Huang et al. · 2017 [cited by applicant]
US 9576814B2 · Wu et al. · 2017 [cited by applicant]
US 9608116B2 · Ching et al. · 2017 [cited by applicant]
US 20170077244A1 · Chang · 2017 [cited by examiner]
US 20190067490A1 · Yang · 2019 [cited by examiner]
US 20200020774A1 · Lee · 2020 [cited by examiner]
US 20210066477A1 · Lee · 2021 [cited by examiner]
US 20220037507A1 · More et al. · 2022 [cited by applicant]
US 20220052203A1 · More · 2022 [cited by applicant]