Semiconductor package including reinforcement structure and methods of forming the same
A semiconductor package includes a package substrate a package substrate including: a substrate core; an upper redistribution layer disposed on a first side of the substrate core; and a lower redistribution layer disposed on an opposing second side of the substrate core; a semiconductor device vertically stacked on and electrically connected to the package substrate; and an upper reinforcement layer embedded in the upper redistribution layer between the semiconductor device and the substrate core, the upper reinforcement layer having a Young's modulus that is higher than a Young's modulus of the upper redistribution layer.
1. A semiconductor package comprising:
a package substrate comprising:
a substrate core;
an upper redistribution layer disposed on a first side of the substrate core and comprising a dielectric structure and metal features that extend through the dielectric structure; and
a lower redistribution layer disposed on an opposing second side of the substrate core;
an interposer vertically stacked on the upper redistribution layer and connected to the metal features;
a semiconductor device vertically stacked on and connected to the interposer; and
an upper reinforcement layer embedded in the upper redistribution layer between the semiconductor device and the substrate core, the upper reinforcement layer having a Young's modulus that is higher than a Young's modulus of the upper redistribution layer, wherein the metal features extend through the upper reinforcement layer.
2. The semiconductor device of claim 1 , wherein a horizontal perimeter of the upper reinforcement layer is disposed outside of a perimeter of the semiconductor device.
3. The semiconductor device of claim 1 , wherein the Young's modulus of the upper reinforcement layer ranges from 14 GPa to 100 GPa.
4. The semiconductor device of claim 1 , wherein the upper reinforcement layer has a thickness that is less than or equal to a thickness of the upper redistribution layer.
5. The semiconductor device of claim 4 , wherein the thickness of the upper reinforcement layer ranges from 10 μm to 164 μm.
6. The semiconductor device of claim 1 , wherein the upper reinforcement layer comprises a dielectric material selected from a silicon, silicon nitride, a ceramic material, or a glass material.
7. The semiconductor device of claim 6 , wherein the metal features comprise bonding pads formed on an upper surface of the reinforcement layer.
8. The semiconductor device of claim 7 , wherein the dielectric structure comprises a build-up film of polymer layers.
9. The semiconductor device of claim 6 , wherein the substrate core comprises a dielectric material selected from a silicon, silicon nitride, a ceramic material, or a glass material.
10. The semiconductor device of claim 1 , further comprising a lower reinforcement layer embedded in the lower redistribution layer, the lower reinforcement layer having a Young's modulus that is higher than a Young's modulus of the upper redistribution layer.
11. The semiconductor device of claim 10 , wherein the upper reinforcement layer comprises a dielectric material selected from a silicon, silicon nitride, a ceramic material, or a glass material.
12. The semiconductor device of claim 10 , wherein the lower reinforcement layer has a thickness that is less than or equal to a thickness of the lower redistribution layer.
13. The semiconductor device of claim 12 , wherein:
the thickness of the lower reinforcement layer ranges from 10 μm to 164 μm; and
a thickness of the upper reinforcement layer ranges from 10 μm to 164 μm.
14. The semiconductor device of claim 10 , wherein:
a horizontal perimeter of the upper reinforcement layer is disposed outside of a perimeter of the semiconductor device; and
a horizontal perimeter of the lower reinforcement layer is disposed outside of the perimeter of the semiconductor device.
15. A semiconductor package comprising:
a package substrate comprising:
a substrate core;
an upper redistribution layer disposed on a first side of the substrate core; and
a lower redistribution layer disposed on an opposing second side of the substrate core and comprising a dielectric structure and metal features that extend through the dielectric structure;
an interposer vertically stacked on and connected to the upper redistribution layer;
a semiconductor device vertically stacked on and connected to the interposer; and
a lower reinforcement layer embedded in the lower redistribution layer facing the semiconductor device, the lower reinforcement layer having a Young's modulus that is higher than a Young's modulus of the lower redistribution layer, wherein the metal features extend through the lower reinforcement layer.
16. The semiconductor device of claim 15 , wherein a horizontal perimeter of the lower reinforcement layer is disposed outside of the perimeter of the semiconductor device.
17. The semiconductor device of claim 15 , wherein:
the lower reinforcement layer comprises a dielectric material selected from a silicon, silicon nitride, a ceramic material, or a glass material; and
the substrate core comprises a dielectric material selected from a silicon, silicon nitride, a ceramic material, or a glass material.
18. The semiconductor device of claim 15 , wherein:
the Young's modulus of the lower reinforcement layer ranges from 14 GPa to 100 GPa; and
a thickness of the lower reinforcement layer ranges from 10 μm to 164 μm.
19. A method of manufacturing a semiconductor package, comprising:
forming package substrate comprising a substrate core, an upper redistribution layer disposed on a first side of the substrate core, and a lower redistribution layer disposed on an opposing second side of the substrate core;
etching the upper redistribution layer to form a first trench;
depositing a reinforcement layer material on the upper redistribution layer and in the first trench;
thinning the reinforcement layer material to form an upper reinforcement layer in the first trench;
forming via structures in the upper reinforcement layer;
forming upper bonding pads on the via structures; and
bonding a semiconductor device to the package substrate, such that a perimeter of the semiconductor device is disposed inside of a perimeter of the first reinforcement layer,
wherein the upper reinforcement layer has a Young's modulus that is greater than a Young's modulus of the upper redistribution layer.
20. The method of claim 19 , further comprising:
etching the lower redistribution layer to form a second trench;
depositing a reinforcement layer material on the lower redistribution layer and in the second trench;
etching back the reinforcement layer material to form a lower reinforcement layer in the second trench;
forming via structures in the lower reinforcement layer; and
forming lower bonding pads on the via structures of the lower reinforcement layer,
wherein the lower reinforcement layer has a Young's modulus that is greater than a Young's modulus of the lower redistribution layer.