Method of manufacturing semiconductor device
The present technology provides a method of manufacturing a semiconductor device. The method includes forming a preliminary source structure, forming a stack structure on the preliminary source structure, the stack structure including a first material layer and a second material layer, forming a preliminary memory layer that penetrates the stack structure, forming a trench passing through the stack structure, forming a first buffer pattern by performing a surface treatment on a portion of the second material layer that is exposed by the trench, and forming a protective layer covering the first buffer pattern.
1. A semiconductor memory device comprising:
a first source layer;
a second source layer over the first source layer;
a third source layer over the second source layer;
a stack structure including a plurality of insulating layers and a plurality of conductive patterns alternately stacked over the third source layer; an insulating spacer in contact with each of a portion of a top surface of the first source layer exposed by the second source layer, a sidewall of the second source layer and a sidewall of the third source layer, the insulating spacer extending along a sidewall of the stack structure;
a channel layer disposed in the stack structure and extending in the first source layer, wherein a portion of the second source layer is in contact with the channel layer; and
a memory layer disposed between the channel layer and each of the stack structure, the first source layer and the third source layer,
wherein an interface between the insulating spacer and the second source layer is further away from the channel layer as the interface is closer to the third source layer.
2. The semiconductor device of claim 1 , wherein the interface between the insulating spacer and the second source layer has a round shape.
3. The semiconductor device of claim 1 , wherein an interface between the insulating spacer and the third source layer is further away from the channel layer as the interface is closer to the stack structure.
4. The semiconductor device of claim 3 , wherein the interface between the insulating spacer and the third source layer has a round shape.
5. The semiconductor device of claim 1 , wherein the portion of the top surface of the first source layer exposed by the second source layer has a round concave shape.
6. The semiconductor device of claim 1 , further comprising:
a conductive source contact extending along a sidewall of the insulating spacer, wherein the conductive source contact is in contact with the portion of the top surface of the first source layer exposed by the second source layer.
7. The semiconductor device of claim 6 , wherein the insulating spacer is disposed between the stack structure and the conductive source contact.
8. A method of manufacturing a semiconductor memory device, the method comprising:
forming a preliminary source structure including a first source layer, a source sacrificial layer over the first source layer and a second source layer over the source sacrificial layer;
forming a hole in the preliminary source structure;
forming a preliminary memory layer on a surface of the hole;
forming a channel layer on the preliminary memory layer;
forming a trench penetrating the second source layer;
forming a buffer pattern by performing a surface treatment of a sidewall of the second source layer through the trench;
forming a protective layer on a sidewall of the trench;
forming a cavity exposing a portion of the preliminary memory layer by removing the source sacrificial layer in a state that the second source layer is protected by the protective layer;
forming an expanded cavity exposing a portion of the channel layer by removing the portion of the preliminary memory layer exposed by the cavity;
removing the protective layer and the buffer pattern to expose the second source layer; and
forming a third source layer in the expanded cavity to be in contact with the portion of the channel layer exposed by the expanded cavity after removing the protective layer.
9. The method of claim 8 , wherein the source sacrificial layer includes a material with an etching selectivity with respective to oxide.
10. The method of claim 8 , wherein the protective layer covers the buffer pattern.
11. A method of manufacturing a semiconductor memory device, the method comprising:
forming a preliminary source structure including a first source layer, a source sacrificial layer over the first source layer and a second source layer over the source sacrificial layer;
forming a stack structure by alternately stacking a plurality of first material layers and a plurality of second material layers on the preliminary source structure;
forming a hole in the preliminary source structure and the stack structure;
forming a preliminary memory layer on a surface of the hole;
forming a channel layer on the preliminary memory layer;
forming a trench penetrating the stack structure and the second source layer;
forming plurality of buffer patterns by performing a surface treatment of a sidewall of the plurality of second material layers through the trench;
forming a protective layer on a sidewall of the trench;
forming a cavity exposing a portion of the preliminary memory layer by removing the source sacrificial layer in a state that the second source layer is protected by the protective layer;
forming an expanded cavity exposing a portion of the channel layer by removing the portion of the preliminary memory layer exposed by the cavity;
removing the protective layer to expose the second source layer;
removing the plurality of buffer patterns to expose the plurality of second material layers;
forming a third source layer in the expanded cavity to be in contact with the portion of the channel layer exposed by the expanded cavity after removing the protective layer and the plurality of buffer patterns; and
replacing the plurality of second material layers with a plurality of conductive patterns through the trench after forming of the third source layer.
12. A method of manufacturing a semiconductor memory device, the method comprising:
forming a preliminary source structure including a first source layer, a source sacrificial layer over the first source layer and a second source layer over the source sacrificial layer;
forming a stack structure by alternately stacking a plurality of first material layers and a plurality of second material layers on the preliminary source structure;
forming a hole in the preliminary source structure and the stack structure;
forming a preliminary memory layer on a surface of the hole;
forming a channel layer on the preliminary memory layer;
forming a trench penetrating the stack structure and the second source layer;
forming plurality of buffer patterns by performing a surface treatment of a sidewall of the plurality of first material layers through the trench;
forming a protective layer on a sidewall of the trench;
forming a cavity exposing a portion of the preliminary memory layer by removing the source sacrificial layer in a state that the second source layer is protected by the protective layer;
forming an expanded cavity exposing a portion of the channel layer by removing the portion of the preliminary memory layer exposed by the cavity;
removing the protective layer to expose the second source layer;
forming a third source layer in the expanded cavity to be in contact with the portion of the channel layer exposed by the expanded cavity after removing the protective layer;
removing the plurality of buffer patterns after the forming of the third source layer; and
replacing the plurality of second material layers with a plurality of conductive patterns through the trench.