Electrically programmable fuse over lateral bipolar transistor
Embodiments of the disclosure provide a circuit structure including an electrically programmable fuse (efuse) and lateral bipolar transistor. A structure of the disclosure includes a lateral bipolar transistor within a semiconductor layer and over a substrate. An insulator layer is over a portion of the semiconductor layer. An efuse structure is within a polycrystalline semiconductor layer and over the insulator layer. The efuse structure is over a current path through the lateral bipolar transistor.
1. A structure comprising:
a lateral bipolar transistor within a semiconductor layer and over a substrate;
an insulator layer over a portion of the semiconductor layer, wherein a separation distance between an emitter of the lateral bipolar transistor and a first sidewall of the insulator layer is larger than a separation distance between a collector of the lateral bipolar transistor and a second sidewall of the insulator layer; and
an electrically programmable fuse (efuse) structure within a polycrystalline semiconductor layer and over the insulator layer, wherein the efuse structure is over a current path through the lateral bipolar transistor, and the insulator layer electrically isolates the efuse structure from the current path.
2. The structure of claim 1 , wherein the separation distance between the emitter of the lateral bipolar transistor and the first sidewall of the insulator is between approximately 0.1 micrometers (μm) and approximately 0.5 μm.
3. The structure of claim 1 , further comprising a resistive semiconductor material vertically between the substrate and the semiconductor layer.
4. The structure of claim 1 , wherein an emitter of the lateral bipolar transistor is coupled to one of an anode and a cathode of the efuse structure.
5. The structure of claim 1 , wherein the insulator layer includes a high-k gate dielectric material.
6. The structure of claim 1 , wherein the semiconductor layer includes a monocrystalline semiconductor.
7. A structure comprising:
a crystalline semiconductor layer over a substrate;
a lateral bipolar transistor defined within the crystalline semiconductor layer;
an insulator layer over a portion of the crystalline semiconductor layer, wherein a separation distance between an emitter of the lateral bipolar transistor and a first sidewall of the insulator layer is larger than a separation distance between a collector of the lateral bipolar transistor and a second sidewall of the insulator layer;
a polycrystalline semiconductor layer on the insulator layer; and
an electrically programmable fuse (efuse) structure defined within the polycrystalline semiconductor layer and over the insulator layer, wherein a vertical thickness of the insulator layer electrically isolates the efuse structure and the lateral bipolar transistor, and wherein the efuse structure is over a current path through the lateral bipolar transistor.
8. The structure of claim 7 , wherein the separation distance between the emitter of the lateral bipolar transistor and the first sidewall of the insulator layer is between approximately 0.1 micrometers (μm) and approximately 0.5 μm.
9. The structure of claim 7 , further comprising a resistive semiconductor material vertically between the substrate and the crystalline semiconductor layer.
10. The structure of claim 7 , wherein an emitter of the lateral bipolar transistor is coupled to one of an anode and a cathode of the efuse structure.
11. The structure of claim 7 , wherein the insulator layer includes a high-k gate dielectric material.
12. A structure comprising:
a first lateral bipolar transistor within a semiconductor layer and over a substrate;
an insulator layer over a portion of the semiconductor layer, wherein a separation distance between an emitter of the first lateral bipolar transistor and a first sidewall of the insulator layer is larger than a separation distance between a collector of the first lateral bipolar transistor and a second sidewall of the insulator layer;
a second lateral bipolar transistor within a polycrystalline semiconductor layer and over the insulator layer; and
an electrically programmable fuse (efuse) structure within the polycrystalline semiconductor layer and over the insulator layer, wherein a cathode of the efuse structure is adjacent one of an emitter and a collector of the second lateral bipolar transistor, and the efuse structure is over a current path through the first lateral bipolar transistor, and the insulator layer electrically isolates the efuse structure from the current path.
13. The structure of claim 12 , wherein the separation distance between the emitter of the first lateral bipolar transistor and the first sidewall of the insulator layer is between approximately 0.1 micrometers (μm) and approximately 0.5 μm.
14. The structure of claim 12 , further comprising a resistive semiconductor material vertically between the substrate and the semiconductor layer.
15. The structure of claim 12 , wherein one of an anode and a cathode of the efuse structure is coupled to each of the first lateral bipolar transistor and the second lateral bipolar transistor.
16. The structure of claim 12 , wherein the insulator layer includes a high-k gate dielectric material.
17. The structure of claim 12 , wherein the semiconductor layer includes a monocrystalline semiconductor.