NAND memory with different pass voltage ramp rates for binary and multi-state memory

1. A non-volatile memory device, comprising:

a control circuit configured to connect to one or more arrays of non-volatile memory cells, each of the one or more arrays having a NAND architecture and configurable to store data in either a single level cell (SLC) format or a multi-level cell (MLC) format for the memory cells, the control circuit comprising:

registers configured to store operating parameters for the one or more memory arrays, the operating parameters including a ramp rate value for applying an unselected word line voltage level for a memory access operation for arrays configured to operate in the SLC format and a ramp rate value for applying an unselected word line voltage level for a memory access operation for arrays configured to operate in the MLC format,

the control circuit configured to:

receive a command to access one or more memory cells along a selected word line corresponding to one or more NAND strings;

determine whether memory cells along the selected word line store data in the SLC format or in the MLC format; and

access the one or more memory cells along the selected word line, where, to access the one or more memory cells, the control circuit is configured to:

bias unselected word lines of the corresponding NAND strings to the unselected word line voltage level at the ramp rate value corresponding to the determined one of the SLC format and the MLC format.

2. The non-volatile memory device of claim 1 , wherein the control circuit is formed on a control die, the non-volatile memory device further comprising:

a memory die including the one or more arrays, the memory die formed separately from and bonded to the control die.

3. The non-volatile memory device of claim 1 , wherein the one or more memory cells along the selected word line are accessed for a program operation.

4. The non-volatile memory device of claim 1 , wherein the one or more memory cells along the selected word line are accessed for a program verify operation.

5. The non-volatile memory device of claim 1 , wherein the one or more memory cells along the selected word line are accessed for a data read operation.

6. The non-volatile memory device of claim 1 , wherein:

the operating parameters further include a ramp rate interval parameter value for applying the unselected word line voltage level for a memory access operation for arrays configured to operate in the SLC format and a ramp rate interval parameter value for applying the unselected word line voltage level for a memory access operation for arrays configured to operate in the MLC format; and

to access the one or more memory cells, the control circuit is configured to bias unselected word lines of the corresponding NAND strings to the unselected word line voltage level for the ramp rate interval parameter value corresponding to the determined one of the SLC format and the MLC format.

7. The non-volatile memory device of claim 6 , wherein the operating parameters for the ramp rate interval parameter value for applying the unselected word line voltage level is a multi-bit value.

8. The non-volatile memory device of claim 1 , wherein the operating parameters for the ramp rate value for applying the unselected word line voltage level is a multi-bit value.

9. The non-volatile memory device of claim 1 , wherein the control circuit further comprises:

one or more charge pump circuits configured to drive the unselected word lines, wherein different ramp rate values correspond to different clock rates for the charge pump circuits.

10. The non-volatile memory device of claim 1 , further comprising:

the one or more arrays, wherein the arrays have a three dimensional NAND architecture.

11. A method, comprising:

receiving a plurality of copies of a non-volatile memory die manufactured according to a design and a set of processing parameter values, the memory die having a NAND architecture;

performing device characterization tests on a sample set of copies of the memory dies;

based on the device characterization tests, determining a ramp rate value for word lines of the array unselected for an access operation of an array of memory cells of the memory die when the array stores data in a multi-level cell format;

based on the device characterization tests, determining a ramp rate value for the word lines of the array unselected for an access operation of the array of memory cells of the memory die when the array stores data in a single level cell format; and

storing, in each of a plurality of the copies of the memory die, a parameter value corresponding to the determined ramp rate value when the array stores data in the multi-level cell format and a parameter value corresponding to the determined ramp rate value when the array stores data in the single level cell format, where, in performing the access operation, the copies of the memory die are configured to ramp up word lines of the array unselected for the access operation to an unselected word line voltage at a ramp rate based on the ramp rate parameter value corresponding to whether the array stores data in the multi-level cell format or stores data in the single level cell format.

12. The method of claim 11 , further comprising:

based on the device characterization tests, determining a ramp rate interval value for the word lines of the array unselected for an access operation of an array of memory cells of the memory die when the array stores data in the multi-level cell format;

based on the device characterization tests, determining a ramp rate interval value for the word lines of the array unselected for an access operation of the array of memory cells of the memory die when the array stores data in the single level cell format; and

storing, in each of the plurality of the copies of the memory die, a parameter value corresponding to the determined ramp rate interval value when the array stores data in the multi-level cell format and a parameter value corresponding to the determined ramp rate interval value when the array stores data in the single level cell format, where, in performing the access operation, the copies of the memory die are configured to ramp up word lines of the array unselected for the access operation to an unselected word line voltage for an interval based on the ramp rate interval parameter value corresponding to whether the array stores data in the multi-level cell format or stores data in the single level cell format.

13. The method of claim 11 , wherein receiving the plurality of copies of the non-volatile memory die includes manufacturing the memory dies according to the design and the set of processing parameter values.

14. The method of claim 11 , wherein the plurality of the memory dies in which the parameter values are stored includes memory dies not in the sample set.

15. The method of claim 11 , further comprising:

subsequent to storing the parameter value corresponding to the determined ramp rate value in the memory dies, assembling one or more of the memory dies into a package.

16. The method of claim 15 , wherein the package further includes one or more memory dies other than the plurality of memory dies.

17. The method of claim 11 , further comprising:

subsequent to storing the parameter value corresponding to the determined ramp rate values, performing the access operation, including determining whether the access is for an array storing data in the multi-level cell format or storing data in the single level cell format and ramping up the word lines unselected for the access operation of the array to an unselected word line voltage at the rate based on the corresponding ramp rate parameter value.

18. The method of claim 11 , wherein the access operation is a programming operation and the unselected word line voltage is a pass voltage for the programming operation.

19. A non-volatile memory device, comprising:

an array of non-volatile memory cells configured to store data in either a single level cell (SLC) format or a multi-level cell format (MLC), comprising:

a plurality of word lines; and

a plurality of NAND strings each having a plurality of memory cells each with a control gate connected to a corresponding one of the word lines; and

one or more control circuits connected to the array, comprising:

registers configured to store operating parameters for the array of non-volatile memory cells, the operating parameters including a ramp rate value for applying an unselected word line voltage level for a memory access operation when the array is configured to store data in the SLC format and a ramp rate value for applying the unselected word line voltage level for the memory access operation when the array is configured to store data in the MLC format; and

a plurality of word line drivers configured, when accessing one or more memory cells along a selected word line, to bias unselected word lines to the unselected word line voltage at the ramp rate value corresponding to the ramp rate parameter value corresponding to whether the array stores data in the MLC format or stores data in the SLC format.

20. The non-volatile memory device of claim 19 , where the operating parameters further include a ramp rate interval value for applying the unselected word line voltage level for a memory access operation when the array is configured to store data in the SLC format and a ramp rate interval value for applying the unselected word line voltage level for the memory access operation when the array is configured to store data in the MLC format, and

the plurality of word line drivers further configured, when accessing one or more memory cells along the selected word line, to bias unselected word lines to the unselected word line voltage, where each of the unselected word lines are ramped up to the unselected word line voltage for a ramp rate interval corresponding to the operating parameter value corresponding to whether the array stores data in the MLC format or stores data in the SLC format.