Granted Patent B2

US 12,411,779 · App. 17/901,846 · Granted Sep 9, 2025

Inventors: Krishna T. Malladi (San Jose, CA); Dimin Niu (Sunnyvale, CA); Hongzhong Zheng (Los Gatos, CA)

Assignee: SAMSUNG ELECTRONICS CO., LTD.

G06F13/1642G06F12/0646G06F2212/251

Abstract

Claims (51)

1. A memory system, comprising:

a data bus configured to transfer data to a memory;

cache media; and

a controller configured to:

receive a data write request to transfer, using the data bus, the data to the memory;

determine that the data comprises one or more characteristics that allows the data bus to perform a different request than the data write request;

communicate, based on one or more characteristics of the data, first information relating to the determining;

store, based on the determining, to the cache media, second information relating to one or more addresses corresponding to at least a portion of the data; and

generate, based on the determining, an indication that the data bus is available for the different request during a cycle time of the data write request.

2. The memory system of claim 1 , wherein the one or more characteristics of the data indicates that the at least a portion of the data comprises sparse data.

3. The memory system of claim 2 , wherein the one or more characteristics of the at least a portion of the data indicates, based on a data granularity, that the data comprises sparse data.

4. The memory system of claim 1 , wherein the data comprises a first value and a second value, wherein the first value is similar to the second value.

5. The memory system of claim 1 , wherein the memory is a first memory;

wherein the cache media is second memory; and

the controller is further configured to process, using the second memory, a data read request for the at least a portion of the data.

6. The memory system of claim 5 , wherein the controller is configured to process, based on the one or more addresses, using the second memory, the data read request for the at least a portion of the data.

7. The memory system of claim 5 , wherein the controller is further configured to:

generate modified data based on the at least a portion of the data; and

store the modified data in the second memory.

8. A method comprising:

receiving, at a controller, a data write request to transfer, using a data bus, data to a memory coupled to the controller using the data bus;

determining that the data comprises one or more characteristics that allows the data bus to perform a different request than the data write request;

communicating, by the controller, based on one or more characteristics of of the data, first information relating to the determining;

storing, based on the determining, to cache media, second information relating to one or more addresses corresponding to at least a portion of the data; and

generating, based on the determining, an indication that the data bus is available for the different request during a cycle time of the data write request.

9. The method of claim 8 , wherein the one or more characteristics indicate that comprises sparse data.

10. The method of claim 9 , wherein the one or more characteristics indicates, based on a data granularity, that the data comprises sparse data.

11. The method of claim 8 , wherein the data comprises a first value and a second value, wherein the first value is similar to the second value.

12. The method of claim 8 , wherein the memory is a first memory;

wherein the cache media is second memory; and

wherein the method further comprises processing, using the second memory, a data read request for the at least a portion of the data.

13. The method of claim 12 , wherein the method further comprises processing, based on the one or more addresses, using the second memory, the data read request for the at least a portion of the data.

14. The method of claim 12 , further comprising:

generating modified data based on the at least a portion of the data; and

storing the modified data in the second memory.

15. An apparatus, comprising:

a controller configured to:

receive a data write request to transfer, using a data bus, data to a memory;

determine that the data comprises one or more characteristics that allows the data bus to perform a different request than the data write request;

communicate, based on one or more characteristics of the data, first information relating to detection the determining;

store, based on the determining, to cache media, second information relating to one or more addresses corresponding to at least a portion of the data; and

generate, based on the determining, an indication that the data bus is available for the different request during a cycle time of the data write request.

16. The apparatus of claim 15 , wherein the one or more characteristics indicate that the data comprises sparse data.

17. The apparatus of claim 15 , wherein the data comprises a first value and a second value, wherein the first value is similar to the second value.

18. The apparatus of claim 15 , wherein the memory is a first memory;

wherein the cache media is second memory; and

the controller is further configured to process, using the second memory, a data read request for the at least a portion of the data.

19. The apparatus of claim 18 , wherein the controller is configured to process, based on the one or more addresses, using the second memory, the data read request for the at least a portion of the data.

20. The apparatus of claim 18 , wherein the controller is configured to:

generate modified data based on the at least a portion of the data; and

store the modified data in the second memory.

Assignments (1)

Continuity (3)

References Cited (45)