IP Library Granted Patent US 12,604,458
Granted Patent B2
US 12,604,458 · App. 17/931,717 · Granted Apr 14, 2026

Apparatus comprising a metal portion in the top portion of capacitor structure, and related methods

Inventors: Harutaka Honda (Hiroshima, JP); Shogo Omiya (Hiroshima, JP); Shoko Norifusa (Hiroshima, JP); Hidekazu Nobuto (Hiroshima, JP)
Assignee: Micron Technology, Inc.
H10B12/31H10B12/033H10B12/09H10B12/50
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Quick Facts
Patent No.
US 12,604,458
App. No.
17/931,717
Granted
Apr 14, 2026
Kind
B2
Abstract

An apparatus includes: a plurality of capacitors each including first and second conductive portions and a dielectric portion therebetween; a first conductive structure containing the plurality of capacitors therein, and electrically coupled to the second conductive portions of the plurality of capacitors; a second conductive structure on a top surface of the first conductive structure; and a third conductive structure on a top surface of the second conductive structure.

Claims (25)

1 . An apparatus comprising:

a plurality of capacitors, each capacitor including first and second conductive portions and a dielectric portion therebetween;

a first conductive structure containing the plurality of capacitors therein, and electrically coupled to the second conductive portions of the plurality of capacitors;

a second conductive structure on a top surface of the first conductive structure, wherein the second conductive structure covers the top surface of the first conductive structure; and

a third conductive structure on a top surface of the second conductive structure.

2 . The apparatus of claim 1 , wherein the second conductive structure and the third conductive structure do not cover a side wall of the capacitors.

3 . The apparatus of claim 1 , wherein the first conductive structure, the second conductive structure and the third conductive structure comprise different materials, respectively.

4 . The apparatus of claim 1 , wherein the first conductive structure comprises impurity-doped polysilicon.

5 . The apparatus of claim 1 , wherein the second conductive structure comprises tungsten nitride.

6 . The apparatus of claim 1 , wherein the third conductive structure comprises tungsten.

7 . The apparatus of claim 1 , wherein the first conductive portion has a pillar shape.

8 . The apparatus of claim 1 , wherein the third conductive structure is formed from an initial tungsten portion formed on the surface of the second conductive structure.

9 . An apparatus comprising:

a memory array including a plurality of memory cells;

a first conductive structure covering the memory array to contain the plurality of memory cells therein, the first conductive structure having a top surface and side surfaces;

a second conductive structure on the top surface of the first conductive structure without covering the side surfaces of the first conductive structure; and

a third conductive structure on a top surface of the second conductive structure without covering the side surfaces of the first conductive structure, wherein the second conductive structure and the third conductive structure comprise different materials.

10 . The apparatus of claim 9 , wherein the first conductive structure, the second conductive structure and the third conductive structure are composed of different materials, respectively.

11 . The apparatus of claim 9 , wherein the first conductive structure comprises impurity-doped polysilicon.

12 . The apparatus of claim 9 , wherein the second conductive structure comprises tungsten nitride and the third conductive structure comprises tungsten.

13 . The apparatus of claim 9 , wherein the plurality of memory cells comprise DRAM memory cells.

14 . The apparatus of claim 13 , wherein the DRAM memory cells comprise capacitors each having first and second conductive portions and the second conductive portion of each capacitor is electrically coupled to the first conductive structure.

15 . The apparatus of claim 14 , wherein the first conductive portion has a pillar shape.

16 . The apparatus of claim 1 , wherein the second conductive structure and the third conductive structure do not cover a sidewall of the first conductive structure.

17 . The apparatus of claim 9 , wherein the third conductive structure is on the top surface of the second conductive structure without covering side surfaces of the second conductive structure.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 13, 2022
From: HONDA, HARUTAKA; OMIYA, SHOGO; NORIFUSA, SHOKO; NOBUTO, HIDEKAZU
To: MICRON TECHNOLOGY, INC
Reel/Frame 061079/0589 →
Continuity (1)
Related Publication 20240090197A1 · Mar 14, 2024
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