Semiconductor backside contact structure with increased contact area
A semiconductor structure having a backside contact structure with increased contact area includes a plurality of source/drain regions within a field effect transistor, each of the plurality of source/drain regions includes a top portion having an inverted V-shaped area. A backside power rail is electrically connected to at least one source/drain region through a backside metal contact. The backside metal contact wraps around a top portion of the at least one source/drain region. A tip of the top portion of the plurality of source/drain regions points towards the backside power rail with the top portion of the at least one source/drain region being in electric contact with the backside metal contact. A first epitaxial layer is in contact with a top portion of at least another source/drain region adjacent to the at least one source/drain region for electrically isolating the at least another source/drain region from the backside power rail.
1. A semiconductor structure, comprising:
a plurality of source/drain regions within a field effect transistor, each of the plurality of source/drain regions including a top portion having a non-curved inverted V-shaped area;
a backside power rail electrically connected to at least one source/drain region through a backside metal contact, the backside metal contact wrapping around a top portion of the at least one source/drain region, a tip of the top portion of the plurality of source/drain regions pointing towards the backside power rail, the top portion of the at least one source/drain region being in electric contact with the backside metal contact; and
a first epitaxial layer being in contact with a top portion of at least another source/drain region adjacent to the at least one source/drain region for electrically isolating the at least another source/drain region from the backside power rail.
2. The semiconductor structure of claim 1 , further comprising:
a front-end-of-line level including the field effect transistor, the front-end-of-line level electrically connected to a back-end-of-line interconnect level located on a first side of the front-end-of-line level;
a plurality of shallow trench isolation regions located between adjacent field effect transistors;
a backside interlayer dielectric surrounding the backside power rail and located on a second side of the front-end-of-line level opposing the first side of the front-end-of-line level; and
a metal contact within an interlevel dielectric layer and in electric contact with a bottom portion of the at least another source/drain region.
3. The semiconductor structure of claim 2 , further comprising:
a carrier wafer in contact with a surface of the back-end-of-line interconnect level opposing the plurality of source/drain regions and the metal contact.
4. The semiconductor structure of claim 1 , wherein the non-curved inverted V-shaped area comprises two opposite sides of each of the plurality of source/drain regions converging to a point in a direction towards a backside of a wafer.
5. The semiconductor structure of claim 4 , wherein a critical dimension of each of the plurality of source/drain regions gradually increases from the top portion of each of the plurality of source/drain regions towards a bottom portion of each of the plurality of source/drain regions opposing the backside of the wafer and being in contact with a channel region of the field effect transistor.
6. The semiconductor structure of claim 1 , wherein the first epitaxial layer being in contact with the top portion of the at least another source/drain region adjacent to the at least one source/drain region comprises a first surface in contact with the backside power rail and a second surface in contact with the top portion of the at least another source/drain region, the second surface being shaped as an inverted V for providing the non-curved inverted V-shaped area to the top portion of the plurality of source/drain regions.
7. The semiconductor structure of claim 1 , wherein the first epitaxial layer comprises an epitaxially grown layer of silicon-germanium.
8. The semiconductor structure of claim 1 , further comprising:
a power delivery network above and in electric contact the backside power rail.
9. The semiconductor structure of claim 1 , wherein the field effect transistor includes at least one of a P-field effect transistor and an N-field effect transistor.
10. The semiconductor structure of claim 1 , wherein the field effect transistor includes a nanosheet field effect transistor.
11. A method of forming a semiconductor structure, comprising:
forming a field effect transistor including a plurality of source/drain regions, each of the plurality of source/drain regions including a top portion having a non-curved inverted V-shaped area;
forming a backside power rail electrically connected to at least one source/drain region through a backside metal contact, the backside metal contact wrapping around a top portion of the at least one source/drain region, a tip of the top portion of the plurality of source/drain regions pointing towards the backside power rail, a top portion of the at least one source/drain region being in electric contact with the backside metal contact; and
forming a first epitaxial layer in contact with a top portion of at least another source/drain region adjacent to the at least one source/drain region for electrically isolating the at least another source/drain region from the backside power rail.
12. The method of claim 11 , further comprising:
forming a front-end-of-line level including the field effect transistor, the front-end-of-line level being electrically connected to a back-end-of-line interconnect level located on a first side of the front-end-of-line level;
forming a plurality of shallow trench isolation regions between adjacent field effect transistors;
forming a backside interlayer dielectric surrounding the backside power rail and on a second side of the front-end-of-line level opposing the first side of the front-end-of-line level; and
forming a metal contact within an interlevel dielectric layer and in electric contact with a bottom portion of the at least another source/drain region.
13. The method of claim 12 , further comprising:
forming a carrier wafer in contact with a surface of the back-end-of-line interconnect level opposing the plurality of source/drain regions and the metal contact.
14. The method of claim 11 , wherein the non-curved inverted V-shaped area comprises two opposite sides of each of the plurality of source/drain regions converging to a point in a direction towards a backside of a wafer.
15. The method of claim 14 , wherein a critical dimension of each of the plurality of source/drain regions gradually increases from the top portion of each of the plurality of source/drain regions towards a bottom portion of each of the plurality of source/drain regions opposing the backside of the wafer and being in contact with a channel region of the field effect transistor.
16. The method of claim 11 , wherein the first epitaxial layer being in contact with the top portion of the at least another source/drain region adjacent to the at least one source/drain region comprises a first surface in contact with the backside power rail and a second surface in contact with the top portion of the at least another source/drain region, the second surface being shaped as an inverted V for providing the non-curved inverted V-shaped area to the top portion of the plurality of source/drain regions.
17. The method of claim 11 , wherein the first epitaxial layer comprises an epitaxially grown layer of silicon-germanium.
18. The method of claim 11 , further comprising:
forming a power delivery network above and in electric contact with the backside power rail.
19. The method of claim 11 , wherein the field effect transistor includes at least one of a P-field effect transistor and an N-field effect transistor.
20. The method of claim 11 , wherein the field effect transistor includes a nanosheet field effect transistor.